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Intel® Xeon™ Processor with 800 MHz

System Bus

Datasheet

Product Features

The Intel® Xeon™ processor with 800 MHz system bus is designed for high-performance

dual-processor workstation and server applications. Based on the Intel® NetBurst™ micro-

architecture and the Hyper-Threading Technology, it is binary compatible with previous Intel

Architecture (IA-32) processors. The Intel Xeon processor with 800 MHz system bus is scalable

to two processors in a multiprocessor system providing exceptional performance for applications

running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*,

and UNIX*.

■ Available at 2.80, 3, 3.20, 3.40, 3.60 GHz

■ 90 nm process technology

■ Dual processing server/workstation support

■ Binary compatible with applications

running on previous members of Intel’s

IA-32 microprocessor line

■ Intel® NetBurst™ micro-architecture

■ Hyper-Threading Technology

■ Hardware support for multithreaded

applications

■ Faster 800 MHz system bus

■ Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

■ Hyper Pipelined Technology

■ Advanced Dynamic Execution

■ Very deep out-of-order execution

■ Enhanced branch prediction

■ Includes 16-KB Level 1 data cache

■ Intel® Extended Memory 64 Technology

■ 1-MB Advanced Transfer Cache (On-die,

full speed Level 2 (L2) Cache) with 8-way

associativity and Error Correcting Code

(ECC)

■ Enables system support of up to 64 GB of

physical memory

■ 144 Streaming SIMD Extensions 2 (SSE2)

instructions

■ 13 Streaming SIMD Extensions 3 (SSE3)

instructions

■ Enhanced floating-point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

■ System Management mode

■ Thermal Monitor

■ Machine Check Architecture (MCA)

■ Demand-Based Switching (DBS) with

Enhanced Intel SpeedStep® Technology

Document Number: 302355-001

June 2004

The Intel Xeon processor with 800 MHz system bus

delivers compute power at unparalleled value and

flexibility for powerful workstations, internet

infrastructure, and departmental server applications. The

Intel NetBurst micro-architecture and Hyper-Threading

Technology deliver outstanding performance and

headroom for peak internet server workloads, resulting in

faster response times, support for more users, and

improved scalability.

Summary of content (96 pages)

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Intel® Xeon™ Processor with 800 MHz System Bus Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Available at 2.80, 3, 3.20, 3.40, 3.
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Intel® Xeon™ Processor with 800 MHz System Bus INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Intel® Xeon™ Processor with 800 MHz System Bus Contents 1.0 Introduction.................................................................................................................................... 9 1.1 1.2 1.3 2.0 Electrical Specifications ............................................................................................................ 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3.0 Package Mechanical Drawings..................................................................
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Intel® Xeon™ Processor with 800 MHz System Bus 6.0 Thermal Specifications .............................................................................................................. 67 6.1 6.2 7.0 Features........................................................................................................................................ 75 7.1 7.2 7.3 8.0 8.3 8.4 8.5 Introduction ...................................................................................................................
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Intel® Xeon™ Processor with 800 MHz System Bus Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Phase Lock Loop (PLL) Filter Requirements ............................................................................. 15 Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0)......... 25 Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.1)......... 25 VCC Static and Transient Tolerance.......................................
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Intel® Xeon™ Processor with 800 MHz System Bus Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 6 Features of the Intel® Xeon™ Processor with 800 MHz System Bus ....................................... 10 Core Frequency to Front Side Bus Multiplier Configuration ....................................................... 14 BSEL[1:0] Frequency Table .......................................................................................................
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Intel® Xeon™ Processor with 800 MHz System Bus Revision History Datasheet Date Revision June 2004 001 Description Initial release.
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Intel® Xeon™ Processor with 800 MHz System Bus 8 Datasheet
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Intel® Xeon™ Processor with 800 MHz System Bus 1.0 Introduction The Intel® Xeon™ processor with 800 MHz system bus is a 32-bit server / workstation processor based on improvements to the Intel NetBurst® microarchitecture. It maintains the tradition of compatibility with IA-32 software and includes features found in the Intel® Xeon™ processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an Execution Trace Cache.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 1. Features of the Intel® Xeon™ Processor with 800 MHz System Bus Intel® Xeon™ processor with 800 MHz system bus No. of Supported Symmetric Agents L2 Advanced Transfer Cache Front Side Bus Frequency Package 1–2 1 MB 800 MHz 604-pin FC-mPGA4 Intel® Xeon™ processor with 800 MHz system bus-based platforms implement independent power planes for each system bus agent.
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Intel® Xeon™ Processor with 800 MHz System Bus • Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology — Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology is the next generation implementation of Geyserville technology which extends power management capabilities of servers and workstations.
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Intel® Xeon™ Processor with 800 MHz System Bus 1.
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Intel® Xeon™ Processor with 800 MHz System Bus 2.0 2.1 Electrical Specifications Power and Ground Pins For clean on-chip power distribution, the processor has 181 VCC (power) and 185 VSS (ground) inputs. All VCC pins must be connected to the processor power plane, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied with the voltage determined by the processor Voltage IDentification (VID) pins.
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Intel® Xeon™ Processor with 800 MHz System Bus 2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the processor. As in previous processor generations, the Intel® Xeon™ processor with 800 MHz system bus core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set during manufacturing. The default setting will be the maximum speed for the processor.
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Intel® Xeon™ Processor with 800 MHz System Bus 2.3.2 Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Intel® Xeon™ processor with 800 MHz system bus. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency).
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Intel® Xeon™ Processor with 800 MHz System Bus Table 12 for the DC specifications for these signals. A minimum voltage is provided in Table 9 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can operate with all supported frequencies.
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Intel® Xeon™ Processor with 800 MHz System Bus Voltage Identification Definition (Sheet 2 of 2) 2,3 Table 4. VID5 VID4 VID3 VID2 VID1 VID0 V CC_MAX VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875 1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000 0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125 1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250 0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375 1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.
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Intel® Xeon™ Processor with 800 MHz System Bus TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 5. Front Side Bus Signal Groups Type Signals1 AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, BR[3:1]#2,3, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#4, BNR#4, BPM[5:0]#, BR0#2,3, DBSY#, DP[3:0]#, DRDY#, HIT#4, HITM#4, LOCK#, MCERR#4 AGTL+ Source Synchronous I/O Synchronous to assoc.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 6 outlines the signals which include on-die termination (RTT) and lists signals which include additional on-die resistance (RL). O.pen drain signals are also included. Table 7 provides signal reference voltages Table 6.
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Intel® Xeon™ Processor with 800 MHz System Bus input buffers. Legacy output THERMTRIP# uses a GTL+ output buffers. All of these Asynchronous GTL+ signals follow the same DC requirements as GTL+ signals, however the outputs are not driven high (during the logical 0-to-1 transition) by the processor. FERR#/PBE#, IERR#, and IGNNE# have now been defined as AGTL+ asynchrnous signals as they include an active p-MOS device.
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Intel® Xeon™ Processor with 800 MHz System Bus At conditions exceeding absolute maximum and minimum ratings, neither functionality nor longterm reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 9. Symbol Voltage and Current Specifications Max Unit Notes 1 1.4000 V 2,3 VID - ICC (max) * 1.25 mΩ V 3, 4, 5, 6, 7 VID step size during a transition ±12.5 mV 8 Total allowable DC load line shift from VID steps 450 mV 9 1.20 1.224 V 10 1.20 1.260 V 10, 11 100 120 A A 6, 19 6, 7, 20 Parameter Min VID range VID range for Intel® Xeon™ processor with 800 MHz system bus 1.
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Intel® Xeon™ Processor with 800 MHz System Bus 7. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See Section 2.11.1 for further details on FMB guidelines. 8. This specification represents the VCC reduction due to each VID transition. See Section 2.4. 9. This specification refers to the potential total reduction of the load line due to VID transitions below the specified VID. 10.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 2. Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0) V RM 10.0 Current 105 Sustained Current Current (A) Sustained [A] 100 95 90 85 80 0.01 0.1 1 10 100 1000 Time Du ra tio n (s ) NOTES: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Figure 3.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 10. VCC Static and Transient Tolerance ICC 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 Voltage Deviation from VID Setting (V) 1,2,3 VCC_Max VCC_Typ VCC_Min VID - 0.000 VID - 0.020 VID - 0.040 VID - 0.006 VID - 0.026 VID - 0.046 VID - 0.013 VID - 0.033 VID - 0.052 VID - 0.019 VID - 0.039 VID - 0.059 VID - 0.025 VID - 0.045 VID - 0.065 VID - 0.031 VID - 0.051 VID - 0.071 VID - 0.038 VID - 0.058 VID - 0.077 VID - 0.
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Intel® Xeon™ Processor with 800 MHz System Bus VCC Static and Transient Tolerance Figure 4. Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 VID - 0.000 V CC Maximum VID - 0.020 VID - 0.040 VID - 0.060 Vcc [V] VID - 0.080 VID - 0.100 VCC Typical VID - 0.120 VID - 0.140 VCC Minimum VID - 0.160 VID - 0.180 VID - 0.200 NOTES: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 5. VCC Overshoot Example Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.11.3 Die Voltage Validation Overshoot events from application testing on processor must meet the specifications in Table 11 when measured across the VCCSENSE and VSSSENSE pins.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 13. AGTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 GTLREF - (0.10 * VTT) V 2,3 VIH Input High Voltage GTLREF + (0.10 * VTT) VTT V 2,4,5 VOH Output High Voltage 0.90 * VTT VTT V 2,5 IOL Output Low Current N/A VTT / (0.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 1 VIL Input Low Voltage 0.0 GTLREF - (0.10 * VTT) V 2,3 VIH Input High Voltage GTLREF + (0.10 * VTT) VTT V 2,4,5 VOH Output High Voltage 0.90 * VTT VTT V 2,5 IOL Output Low Current N/A VTT / (0.
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Intel® Xeon™ Processor with 800 MHz System Bus 3.0 Mechanical Specifications The Intel® Xeon™ processor with 800 MHz system bus is packaged in Flip Chip Micro Pin Grid Array (FC-mPGA4) package that interfaces to the baseboard via an mPGA604 socket. The package consists of a processor core mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 7.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 8.
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Intel® Xeon™ Processor with 800 MHz System Bus 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 8 for keepout zones. 3.
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Intel® Xeon™ Processor with 800 MHz System Bus 3.4 Package Handling Guidelines Table 18 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 18. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 lbf 1, 4, 5 Tensile 156 N 35 lbf 2, 4, 5 Torque 8 N-m 70 lbf-in 3, 4, 5 NOTES: 1.
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Intel® Xeon™ Processor with 800 MHz System Bus 3.8 Processor Markings Figure 9 shows the topside markings and Figure 10 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon™ processor with 800 MHz system bus. Figure 9. Processor Top-Side Markings (Example) Processor Name i(m) ©’03 2D Matrix Includes ATPO and Serial Number (front end mark) ATPO Serial Number Pin 1 Indicator NOTES: 1. All characters will be in upper case. 2.
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Intel® Xeon™ Processor with 800 MHz System Bus 3.9 Processor Pinout Coordinates Figure 11 and Figure 12 show the top and bottom view of the processor pin coordinates, respectively. The coordinates are referred to throughout the document to identify processor pins. Figure 11.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 12.
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Intel® Xeon™ Processor with 800 MHz System Bus 4.0 Signal Definitions 4.1 Signal Definitions Table 20. Signal Definitions (Sheet 1 of 9) Name A[35:3]# Type Description Notes I/O A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the front side bus.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name BINIT# Signal Definitions (Sheet 2 of 9) Type I/O Description BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name BR0# BR[1:3]# 1 Signal Definitions (Sheet 3 of 9) Type Description Notes I/O BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. The tables below provide the rotating interconnect between the processor and bus signals for 2-way systems.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name DBI[3:0]# Signal Definitions (Sheet 4 of 9) Type Description Notes I/O DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Signal Definitions (Sheet 5 of 9) Name Type Description Notes FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name LINT[1:0] Signal Definitions (Sheet 6 of 9) Type Description Notes I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium® processor.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name REQ[4:0]# RESET# Signal Definitions (Sheet 7 of 9) Type Description Notes I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front side bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name Signal Definitions (Sheet 8 of 9) Type Description TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO O TDO (Test Data Out) transfers serial test data out of the processor.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Name Signal Definitions (Sheet 9 of 9) Type Description VIDPWRGD I The processor requires this input to determine that the supply voltage for BSEL[1:0] and VID[5:0] is stable and within specification. VSSA I VSSA provides an isolated, internal ground for internal PLL’s. Do not connect directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a discrete filter circuit.
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Intel® Xeon™ Processor with 800 MHz System Bus 48 Datasheet
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Intel® Xeon™ Processor with 800 MHz System Bus 5.0 Pin List 5.1 Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments This section provides sorted pin lists in Table 21 and Table 22. Table 21 is a listing of all processor pins ordered alphabetically by pin name. Table 22 is a listing of all processor pins ordered by pin number.
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Intel® Xeon™ Processor with 800 MHz System Bus 5.1.1 Pin Listing by Pin Name Table 21. Pin Listing by Pin Name (Sheet 1 of 8) Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 2 of 8) Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 3 of 8) Signal Buffer Type Direction D7 Common Clk I/O N/C Y29 N/C N/C TDI C24 TAP Input N/C AA28 N/C N/C TDO E25 TAP Output Pin Name MCERR# Pin No. Pin Name TCK Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Name VCC Pin Listing by Pin Name (Sheet 4 of 8) Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Name Pin Listing by Pin Name (Sheet 5 of 8) Pin No. Signal Buffer Type Pin Name VCC Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 6 of 8) Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Name VSS Pin Listing by Pin Name (Sheet 7 of 8) Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Name Pin Listing by Pin Name (Sheet 8 of 8) Pin No. Signal Buffer Type Direction Pin Name VSS Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus 5.1.2 Pin Listing by Pin Number Table 22. Pin Listing by Pin Number (Sheet 1 of 8) Pin No. Pin Name Signal Buffer Type Direction Output A1 VID5 Power/Other A2 VCC Power/Other A3 SKTOCC# Power/Other A4 VTT Power/Other Output Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 2 of 8) Pin No. Pin Name Signal Buffer Type Direction Source Sync I/O D24 D25 Reserved Reserved Reserved D26 VSSSENSE Power/Other Output C15 A15# C16 VCC Power/Other C17 A8# Source Sync I/O C18 A6# Source Sync I/O C19 VSS Power/Other C20 REQ3# Source Sync C21 REQ2# Source Sync Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No. Pin Listing by Pin Number (Sheet 3 of 8) Pin Name Signal Buffer Type Direction Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No. Pin Listing by Pin Number (Sheet 4 of 8) Pin Name Signal Buffer Type J28 VCC Power/Other J29 VSS Power/Other J30 VCC Power/Other J31 VSS Power/Other K1 VCC Power/Other K2 VSS K3 VCC K4 VSS K5 VCC Direction Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No. Pin Listing by Pin Number (Sheet 5 of 8) Pin Name Signal Buffer Type Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No. V26 Pin Listing by Pin Number (Sheet 6 of 8) Pin Name Signal Buffer Type Direction Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No. AA26 Pin Listing by Pin Number (Sheet 7 of 8) Pin Name VCC Signal Buffer Type Direction Power/Other Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin No.
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Intel® Xeon™ Processor with 800 MHz System Bus 66 Datasheet
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Intel® Xeon™ Processor with 800 MHz System Bus 6.0 Thermal Specifications 6.1 Package Thermal Specifications The Intel® Xeon™ processor with 800 MHz system bus requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
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Intel® Xeon™ Processor with 800 MHz System Bus will violate the thermal specifications and may result in permanent damage to the processor. Intel has developed these thermal profiles to allow OEMs to choose the thermal solution and environmental parameters that best suit their platform implementation. Refer to the appropriate thermal/mechanical design guide for details on system thermal solution design, thermal profiles, and environmental considerations.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 13. Intel® Xeon™ Processor with 800 MHz System Bus Thermal Profiles A and B 90 TCASE MAX_B @ 80 TDP TCASE_MAX_A @ 70 TDP Thermal Profile B Y = 0.35 * x + 44 60 TCASE_MAX @ 50 Pcontrol_base Thermal Profile A Y = 0.28 * x + 43 Tcase [°C] 40 TCASE_MAX_B is a thermal solution design point. In actuality, units will not exceed TCASE_MAX_A due to TCC activation.
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Intel® Xeon™ Processor with 800 MHz System Bus Table 24. Intel® Xeon™ Processor with 800 MHz System Bus Thermal Profile A Power [W] PCONTROL_BASE_A = 25 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Table 25.
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Intel® Xeon™ Processor with 800 MHz System Bus 6.1.2 Thermal Metrology The maximum case temperatures (TCASE) are specified in Table 24, Table 25 and measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 14 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate thermal/mechanical design guide. Figure 14. Case Temperature (TCASE) Measurement Location 21.
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Intel® Xeon™ Processor with 800 MHz System Bus specification and affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate thermal/mechanical design guide for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified.
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Intel® Xeon™ Processor with 800 MHz System Bus FORCEPR# can be used to thermally protect other system components. To use the VR as an example, when the FORCEPR# pin is asserted, the TCC circuit in the processor will activate, reducing the current consumption of the processor and the corresponding temperature of the VR. If should be noted that assertion of the FORCEPR# does not automatically assert PROCHOT#.
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Intel® Xeon™ Processor with 800 MHz System Bus 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW = IS * (e qVD/nkT - 1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature.
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Intel® Xeon™ Processor with 800 MHz System Bus 7.0 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Intel® Xeon™ processor with 800 MHz system bus samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 15. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
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Intel® Xeon™ Processor with 800 MHz System Bus 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT Power-Down State HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT instruction, that logical processor is halted; however, the other processor continues normal operation.
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Intel® Xeon™ Processor with 800 MHz System Bus Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the front side bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the ° state.
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Intel® Xeon™ Processor with 800 MHz System Bus In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the front side bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
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Intel® Xeon™ Processor with 800 MHz System Bus 8.0 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon™ processor with 800 MHz system bus will be offered as an Intel boxed processor.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 17. 2U Passive CEK Heatsink Figure 18.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 19. Passive Intel® Xeon™ Processor with 800 MHz System Bus Thermal Solution (2U and larger) Heat sink screw springs Heat sink screws Heat sink Heat sink standoffs Thermal Interface Material Motherboard and processor Protective Tape CEK spring Chassis pan NOTES: 1. The heatsink in this image is for reference only, and may not represent any of the actual boxed processor heatsinks. 2.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 20.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 21.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 22.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 23.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 24.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 25.
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Intel® Xeon™ Processor with 800 MHz System Bus Figure 26.
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Intel® Xeon™ Processor with 800 MHz System Bus 8.2.2 Boxed Processor Heatsink Weight 8.2.2.1 Thermal Solution Weight The 2U passive and 2U+ active heatsink solutions will not exceed a mass of 1050 grams. Note that this is per processor, so a dual processor system will have up to 2100 grams total mass in the heatsinks. The 1U CEK heatsink will not exceed a mass of 700 grams, for a total of 1400 grams in a dual processor system.
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Intel® Xeon™ Processor with 800 MHz System Bus A new 4-pin PWM/T-diode controlled active fan heatsink solution will replace the 3-pin thermistor controlled solution after initial boxed Intel® Xeon™ processor with 800 MHz system bus introduction. This new solution is being offered to help provide better control over pedestal chassis acoustics. This is achieved though more accurate measurement of processor die temperature through the processor’s temperature diode (T-diode).
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Intel® Xeon™ Processor with 800 MHz System Bus Table 31. Fan Cable Connector Pinout (3-pin active CEK heatsink) Pin Number Signal 1 Ground Black 2 Power: (+12 V) Yellow 3 Sense: 2 pulses per revolution Green Figure 28. Fan Cable Connector Pinout (4-pin active CEK heatsink) Table 32. Fan Cable Connector Pinout (4-pin active CEK heatsink) Table 33.
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Intel® Xeon™ Processor with 800 MHz System Bus 8.4 Thermal Specifications This section describes the cooling requirements of the heatsink solution used by the boxed processor. 8.4.1 Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in three product configurations. Each configuration will require unique design considerations.
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Intel® Xeon™ Processor with 800 MHz System Bus 8.5 Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration, due to the weight of the heatsink required to cool the processor. The board must not bend beyond specification in order to avoid damage. The boxed processor contains the components necessary to solve both issues.
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Intel® Xeon™ Processor with 800 MHz System Bus 94 Datasheet
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Intel® Xeon™ Processor with 800 MHz System Bus 9.0 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool specifications. Section 1.2 provides collateral details. 9.1 Debug Port System Requirements The Intel® Xeon™ processor with 800 MHz system bus debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
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Intel® Xeon™ Processor with 800 MHz System Bus 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer.