Quad-Core Intel® Xeon® Processor 3200 Series Datasheet —on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology± January 2007 Document Number: 316133-001
Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
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Contents 1 Introduction ............................................................................................................11 1.1 Terminology......................................................................................................11 1.1.1 Processor Terminology ............................................................................12 1.2 References........................................................................................................
.3 5.2.5 THERMTRIP# Signal ............................................................................... 79 Platform Environment Control Interface (PECI) ...................................................... 80 5.3.1 Introduction .......................................................................................... 80 5.3.1.1 Key Difference with Legacy Diode-Based Thermal Management ....... 80 5.3.2 PECI Specifications ................................................................................
Figures 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 5-1 5-2 5-3 5-4 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 6 VCC Static and Transient Tolerance.......................................................................22 VCC Overshoot Example Waveform .......................................................................23 Differential Clock Waveform ................................................................................31 Differential Clock Crosspoint Specification ............................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 6-1 7-1 References ....................................................................................................... 13 Voltage Identification Definition........................................................................... 17 Absolute Maximum and Minimum Ratings ............................................................. 19 Voltage and Current Specifications..............
Revision History Revision Number -001 8 Description • Initial release Date January 2007 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Quad-Core Intel Xeon Processor 3200 Series Features • Optimized for 32-bit applications running on advanced 32-bit operating systems • Available at 2.13 GHz and 2.
Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Introduction 1 Introduction The Quad-Core Intel® Xeon® Processor 3200 Series are the first server quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. They are 64-bit processors that maintain compatibility with IA-32 software.
Introduction 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: • Quad-Core Intel Xeon Processor 3200 Series - Quad core processor in the FCLGA6 package with a 2x4 MB L2 cache. • Processor — For this document, the term processor is the generic form of the Quad-Core Intel® Xeon® Processor 3200 Series. The processor is a single package that contains one or more execution units. • Keep-out zone — The area on or near the processor that system design can not utilize.
Introduction • Enhanced Intel Technology SpeedStep® Technology — Enhanced Intel Technology SpeedStep® Technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).
Introduction 14 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2-1. VID6 VID5 Voltage Identification Definition VID4 VID3 VID2 VID1 VCC_MAX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 2-2 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.5.2 DC Voltage and Current Specification Table 2-3. Voltage and Current Specifications Symbol VID Range VCC Parameter VID Processor Number X3220 X3210 VCC for 775_VR_CONFIG_05B 2.40 GHz 2.13 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC ICC Processor Number X3220 X3210 ISGNT Processor Number X3220 X3210 Notes1, 2 Min Typ Max Unit 0.8500 — 1.5 V 3 Refer to Table 2-4 and Figure 2-1 V 4, 5, 6 V — 1.10 — - 5% 1.
Electrical Specifications 13.This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. Table 2-4.
Electrical Specifications Figure 2-1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 Vcc [V] VID - 0.100 Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 Vcc Minimum VID - 0.163 VID - 0.175 VID - 0.188 VID - 0.200 VID - 0.213 VID - 0.225 Notes: 1.
Electrical Specifications Figure 2-2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.5.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 2-5 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[3:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications . Table 2-7.
Electrical Specifications 2.6.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 2-9. GTL+ Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 GTLREF – 0.10 V 2, 3 GTLREF + 0.10 VTT + 0.10 V 3, 4, 5 Output High Voltage VTT – 0.
Electrical Specifications Table 2-11. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 3, 4, 5 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 3, 5,6 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications.
Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 2-16. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.30 N/A N/A V 2-3 2 VH Input High Voltage N/A N/A 1.15 V 2-3 2 0.300 N/A 0.550 V 2-3, 2-4 3, 4, 5 VCROSS(abs) Absolute Crossing Point Range of Crossing Points N/A N/A 0.140 V 2-3, 2-4 - VOS Overshoot N/A N/A 1.4 V 2-3 6 VUS Undershoot -0.
Electrical Specifications Figure 2-3. Differential Clock Waveform CLK 0 V CROSS Median + 75 mV VCROSS Max 500 mV Median - 75 mV VCROSS Min 300 mV VCROSS median VCROSS VCROSS CLK 1 High Time median Low Time Period Figure 2-4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.
Electrical Specifications 32 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications • Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-6 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-6.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1. 44 Alphabetical Land Assignments (Sheet 1 of 21) Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Land Name Alphabetical Land Assignments (Sheet 3 of 21) Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 46 Alphabetical Land Assignments (Sheet 5 of 21) Land Name Land # Signal Buffer Type FC30 U3 FC31 FC32 FC33 FC34 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 7 of 21) Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 48 Alphabetical Land Assignments (Sheet 9 of 21) Land Name Land # Signal Buffer Type VCC AJ11 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 11 of 21) Land Name Land # Signal Buffer Type VCC J24 Power/Other VCC J25 Power/Other VCC J26 VCC J27 VCC VCC VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 15 of 21) Table 4-1.
Land Listing and Signal Descriptions Table 4-1. 52 Alphabetical Land Assignments (Sheet 17 of 21) Land Name Land # Signal Buffer Type VSS AN23 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments (Sheet 19 of 21) Land Name Land # Signal Buffer Type VSS L28 VSS L29 VSS VSS VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Land # Numerical Land Assignment (Sheet 1 of 21) Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 56 Numerical Land Assignment (Sheet 3 of 21) Land # Land Name C18 D54# Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 5 of 21) Land # Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 58 Numerical Land Assignment (Sheet 7 of 21) Land # Land Name Signal Buffer Type H26 VSS H27 H28 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 9 of 21) Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 60 Numerical Land Assignment (Sheet 11 of 21) Land # Land Name Signal Buffer Type U8 VCC U23 U24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 13 of 21) Land # Land Name AB5 A24# AB6 A17# Signal Buffer Type Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 62 Numerical Land Assignment (Sheet 15 of 21) Land # Land Name Signal Buffer Type AF3 VSS AF4 AF5 AF6 AF7 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment (Sheet 17 of 21) Land # Land Name Signal Buffer Type AH21 VCC AH22 VCC AH23 AH24 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. 64 Numerical Land Assignment (Sheet 19 of 21) Land # Land Name Signal Buffer Type AL7 VSS AL8 AL9 Table 4-2.
Land Listing and Signal Descriptions Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 6) Name A[35:3]# A20M# Type Input/ Output Description 236-byte physical memory address space. In A[35:3]# (Address) define a sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 6) Type Description BR0# Name Input/ Output BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. BSEL[2:0] Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 6) Name Description Input DRDY# Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# Input/ Output DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 6) Type Description IGNNE# Name Input IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 6) Name RESET# Type Description Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will de-assert their outputs within two clocks.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 6) Name Type Description TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
Land Listing and Signal Descriptions 72 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for 105 W Processor Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.3 28 48.3 56 53.4 84 58.4 2 43.7 30 48.7 58 53.8 86 58.8 4 44.0 32 49.1 60 54.1 88 59.1 6 44.4 34 49.4 62 54.5 90 59.5 Figure 5-1. 8 44.7 36 49.8 64 54.9 92 59.9 10 45.1 38 50.1 66 55.2 94 60.3 12 45.5 40 50.5 68 55.4 96 60.6 14 45.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-2 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Quad-Core Intel® Xeon® Processor 3200 Series Thermal and Mechanical Design Guidelines.
Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.
Thermal Specifications and Design Considerations voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-3 for an illustration of this ordering. Figure 5-3.
Thermal Specifications and Design Considerations the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the OnDemand mode. 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature.
Thermal Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction Platform Environment Control Interface (PECI) offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification.
Thermal Specifications and Design Considerations 82 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features While in Stop-Grant state, the processor will process a FSB snoop. 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Extended HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-3. Space Requirements for the Boxed Processor (Top View) Notes: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4. Space Requirements for the Boxed Processor (Overall View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams.
Boxed Processor Specifications 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly. 7.2 Electrical Requirements 7.2.1 Fan Heatsink Power Supply The boxed processor's fan heatsink requires a +12 V power supply.
Boxed Processor Specifications Table 7-1. Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit +12 V: 12-volt fan power supply 11.4 12 12.6 V IC: Notes - - Maximum fan steady-state current draw Average fan steady-state current draw Maximum fan start-up current draw Fan start-up current draw maximum duration — — — — 1.2 0.5 2.2 1.0 — — — — A A A Second SENSE: SENSE frequency — 2 — pulses per fan revolution 1 CONTROL 21 25 28 Hz 2, 3 Notes: 1.
Boxed Processor Specifications properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 7-7 and Figure 7-8 illustrate an acceptable airspace clearance for the fan heatsink.
Boxed Processor Specifications Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) 7.3.2 Fan Speed Control Operation The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty cycle of the CONTROL signal on the 4th pin (see Table 7-1).
Boxed Processor Specifications 94 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 96 Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
