User's Manual

Ver.1.0

REG21 (wired-communication setting 2[flow control], low power stand-by mode, extended stand-by time)

[Default: 09H]

Bits 7 to 4: Extended Stand-by time

Bit 7 Bit 6 Bit5 Bit4 Extended Stand-by time

0 0 0 0 0 (0x20): Default

0 0 0 1 20ms (1x20)

0 0 1 0 40ms (2x20)

1 1 1 0 280ms (14x20)

1 1 1 1 300ms (15x20)

When the FDP03 receives data packet that destination address is matched at the setting of the REG18 is

“Enabling destination address check at reception”, the time duration of the Stand-by mode is extended. If the data

packet is set by broadcasting mode and/or the setting of the REG18 is “Disabling group address check at reception”, the

time duration of the Stand-by mode is NOT extended. When “Extended Stand-by time” is set to 0ms, the FDP03

becomes “Sleep” mode right after it sends back ACK packet.

Bit 3: No used

Bit 2: Low power stand-by mode

0 Normal Operation Mode (Default)

1 Low Power Stand-by Mode

By setting “1” for the bit 2 of REG21 and re-booting the FDP03, operation mode becomes “Low power

stand-by mode”. It is also turned “low power operation mode” after returning from the “Power down

mode”. Time duration of the Stand-by and sleep mode are set by REG22 and REG25, respectively.

Bit 1: Hardware flow control

0 Disabling hardware flow control (default)

1 Enabling hardware flow control

This register can define validity of hardware flow control. If hardware flow control is enabled, the setting

of the FDP03 should be same as that of the external device that connected to the FDP03. On the FDP03,

make the same setting of this register as the flow control setting on the external equipment connected to the

FDP03.

Hardware flow control is available by connecting control cables to the RTS and CTS pins.

Data flow may not stop immediately right after the hardware flow

control vans the data flow if the software is written by PC. In such a

case, some data from the PC may be lost.

Bit 0: Not used