User's Manual

Page 152 FRH-SD07TU/TB Manual
8.4.3 Output Forma t
rmat.
4 bits indicates which data frame is output from the
th the frame address and status signal
re the MSB first output.
s shown in the next paragraph of OUTPUT TIMING, these data are the clock synchronous
serial output, which is latched by rising edge of the LOAD signal at the end of each frame.
irst bit Last bit
D1 D0
Signals are output in the following fo
One frame consists of 12 bits. The first
status monitor circuit (frame address), and the following 8 bits are the actual status signal.
Frames are repeatedly output from Address 0 to 4. Bo
a
A

F
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2
Frame Address (4bits) Status signal bits (8bits)
ur t Fig e C–1: Output Forma
Rev. 050415-01.1