Owner Manual User guide

ALGORITHMS
32 bit Shift Register
The shift register accepts a logic signal at its input and shifts that value
sequentially through the 32 outputs, starting at output 1 and ending in
output 32. You can think of this as a of 32-tap logic delay.
Logic data is shifted to the next output every time a 1/16
th
note clock
occurs.
Shift register outputs are expressed as an “S” followed by a two-digit
value indicating the output number.