User Manual

XScopes
User’s Manual
DS-XScopes-3.5 – December, 2014 Page | 25
3.9 I2C Sniffer
Connect SDA to Bit 0, SCL to Bit 1
The XScope implements the I2C sniffing in a bit-bang fashion. The maximum tested clock frequency is 400kHz (Standard
I2C Fast Speed). As the data is decoded, the data in HEX will appear on the screen, accompanied by a symbol:
When the Master initiates a read, < is an ACK and ( is a NACK
When the Master initiates a write, > is an ACK and ) is a NACK
Subsequent data in the frame will be accompanied by + for ACK or a - for NACK.
There are 16 pages of data, each page shows 64 bytes => the total memory for the I2C sniffer is 1024 bytes.
Example communicating to a Si570 Programmable oscillator:
55> 07+ (Master initiates Write to slave 55, byte address 7)
55< 05+ 42+ B6+ 04+ 79+ 9A- (Master initiates Read to slave 55, then reads 6 bytes)
3.10 UART Sniffer
Connect RX to Bit 2, TX to Bit 3
The XScope can decode both the TX and RX lines of the UART at the standard baud rates, and with selectable data bits:
5,6,7,8 Data bits / 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 bps
When the sniffer begins, the screen is split in two, the left side is used for the RX line,
and the right side is used for the TX line. Each side can show 40 bytes per page. With
16 pages, a total of 640 bytes can be stored for each decoded line.
3.11 SPI Sniffer
Connect the Slave Select to Bit 4, MOSI to Bit 5, MISO to Bit 6, SCK to Bit 7
The XScope can decode both the MOSI and MISO lines of an SPI bus. The
SPI's MOSI pin decoding is done in hardware, so it can decode data at high
speed (up to 8MHz), but the SPI's MISO pin decoding is implemented in
software using bit-banging, the maximum clock is 439kHz. Decoding starts
when a falling edge on the SS pin is detected.
The screen is split in two, the left side is used for the MOSI line, and the right
side is used for the MISO line. Each side can show 40 bytes per page. With 16
pages, a total of 640 bytes can be stored for each decoded line. Table 7 shows the SPI configuration.
Configuration
Leading edge
Trailing edge
CPOL CPHA
Rising, sample
Falling, setup
CPOL CPHA .
Rising, setup
Falling, sample
CPOL CPHA
Falling, sample
Rising, setup
CPOL CPHA .
Falling, setup
Rising, sample
Table 7: SPI Configuration
Figure 52: UART Sniffer screen