User's Manual

GS1500M DATA SHEET
PRELIMINARY GAINSPAN CONFIDENTIAL PAGE 14 OF 43
► Two clock design:
• APB bus clock for bus interface and registers.
• Serial input clock for core logic.
► Support of external EEPROM or other non-volatile memory.
► Programmable choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or
National Semiconductor Microwire.
► Programmable control of the serial bit rate of the data transfer in serial-master mode of operation.
► Programmable phase and polarity of the bit rate clock.
► Programmable transfer modes to perform transmit and receive, transmit only, receive only and
EEPROM read transfers.
► Programmable data word size (8, 16, 24 & 32 bits) for each data transfer.
► Transmit and receive FIFO buffer depth 8 words (of the selected size).
► Configurable number of slave select outputs in serial-master mode of operation: 1 to 4 serial slave-
select output signals can be generated.
► Combined interrupt line with independent masking of interrupts.
► Transmit FIFO overflow, transmit FIFO empty, transmit FIFO underflow, receive FIFO full,
receive FIFO underflow, receive FIFO overflow, and receive FIFO timeout interrupts.
► Transmit FIFO empty and receive FIFO full interrupts provide programmable threshold values.
Both SPI blocks are configured to provide a FIFO depth of four entries.
The SPI master interface can be used to access external sensor devices, and EEPROM containing system
parameters, under software control while the SPI slave interface can be used to provide control of the
GS1500M from an external CPU.
SPI chip select (MPSISI_CS0 or MPSI_CS1) signals frame each data word. If the chip select is required
to remain asserted for multiple data words, then a GPIO pin should be used for the chip select instead of
the SPI chip select signals. For clock architecture and rates, please refer to section 7.1 Clock
Architecture of GS1011 Peripheral and Register Description [2]. For other SPI Interface Timing, please
refer to section 4.7.
2.3.2 I
2
C
The I
2
C block provides a two-wire I
2
C serial interface. It provides the following features:
► 32-bit AMBA APB interface to allow access to data, control, and status Information by the host
processor.
► Serial 2-wire I
2
C bus, compliant to the I
2
C Bus Specification Version 2.1.
► Supports only one transfer in Standard mode (100 Kb/s) and fast speed mode with a bit rate of up
to 392 Kb/s.
► Supports Multi-Master System Architecture through I
2
C bus SCL line Synchronization and
Arbitration.
► Transmitter and Receiver: The I
2
C block can act as the Transmitter or Receiver depending on the
operation being performed.
► Master or slave I
2
C operation.
► 7- or 10-bit addressing.