User's Manual

GS1500M DATA SHEET
PRELIMINARY GAINSPAN CONFIDENTIAL PAGE 33 OF 43
4.8.3 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0
Figure 4-5: timing diagram, Master mode, SPO=1, SPH=0.
Parameter
Description
Minimum
Maximum
Unit
tSSetup
Minimum time between falling
edge of select line and first falling
edge of SPI clock.
1
MSPI
clock
period
tTxdDelay
Delay in Master asserting TX line
after falling edge of Select line.
2 core SPI
clock
periods +
3 ns
mixed
tRxdSetup
Time before falling edge of SPI
clock by which received data must
be ready.
30 ns
tRxdHold
Time for which received data
must be stable after falling edge
of SPI clock.
10 ns
tSSHold
Time for which the Select line will
be held low after the sampling
edge for the final bit to be
transferred.
1
MSPI
clock
period
Table 4-16: timing parameters, Master mode, SPO=1, SPH=0.