User's Manual

GS2011M Low Power WiFi Module Data Sheet GS2011M Architecture
Wireless LAN and System Control Subsystem
GS2011M-DS-001211, Release 0.9 Confidential Preliminary 27
This counter is automatically reset by power-on-reset.
This counter wraps around (returns to “all-0” once it has reached the highest possible
“all-1” value).
RTC I/O
There are three (3) RTC I/O (0, 1,2) that can be used to control external devices, such as
sensors or wake up the module based on external events or devices.
DC_DC_CNTL
During RTC Power-on-Reset (e.g. when the battery is first connected), the dc_dc_cntl pin
is held low; it goes high to indicate completion of RTC power-on-reset. This pin can be
used as an enable into an external device such as voltage regulator. The dc_dc_cntl also is
held low when module is in standby and goes high to indicate wake up from standby.
GS2011M Peripherals
SDIO Interface
The SDIO interface is a full / high speed SDIO device controller. The Controller supports
SPI, 1-bit SD and 4-bit SD bus mode. The SDIO block has an AHB interface, which allows
the CPU to configure the operational registers residing inside the AHB Slave core. The CIS
and CSA area is located inside the internal memory of CPU subsystem. The SDIO Registers
(CCCR and FBR) are programmed by both the SD Host (through the SD Bus) and CPU
(through the AHB bus) via Operational registers. The SDIO block implements the AHB
master to initiate transfers to and from the system memory autonomously.
During the normal initialization and interrogation of the card by the SD Host, the card will
identify itself as an SDIO device. The SD Host software will obtain the card information in
a tuple (linked list) format and determine if that card’s I/O function(s) are acceptable to
activate. If the Card is acceptable, it will be allowed to power up fully and start the I/O
function(s) built into it.
The SDIO interface implements Function 1 in addition to the default Function 0. All
application data transfers are done through the Function 1.
The primary features of this interface are:
• Meets SDIO card specification version 2.0
• Conforms to AHB specification
• Host clock rate variable between 0 and 40 MHz
• All SD bus modes supported including SPI, 1 and 4 bit SD
NOTE: Tested with current test platform up to 33 MHz.