User's Manual
Table Of Contents
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Theory of Operation DC Power Distribution
Page: 4-16 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
4.5.2.5 External I/O Board Power
5 Vdc and +3.3 Vdc are supplied to the external I/O board is received at connector P1 from
controller board connector J3.
4.5.2.6 Front Panel Board
Power for front panel board is received at connector J1 from controller board connector J4.
• +5 Vdc for the front panel board is received at connector J1 pins 1 and 2.
• +5 Vdc for the back light is received at connector J1 pins 46 through 50.
• +3.3 Vdc for the front panel board is received at connector J1 pins 24 and 25.
4.5.3 Analog Deck Power
All power for the analog (upper) deck of the exciter enters the UDC interface board at J4.
From the UDC interface board J2 the power is fed to the down converter board J8, PLL
board J1, and up converter board J3 by a ribbon cable which parallels the connectors.
4.5.3.1 UDC Interface Board Power
The power supply module supplies +/- 15 Vdc to the UDC (up/down converter) Interface
board via connector J4. See Table 4-3 on page 14 for a list of pin assignments for J4.
+15 Vdc is fed to an on-board switching dc to dc converter and produces +8 Vdc. +8 Vdc
is fed to a linear regulator which produces +5 Vdc. +5 Vdc is fed to a linear regulator which
produces +3.3 Vdc.
The +/-15 Vdc and the +8 Vdc voltages are fed from the UDC interface board J2 to the
down converter board J8, PLL board J1, and up converter board J3 by a ribbon cable which
parallels the connectors. The output amplifier receives +/-15 Vdc at J5 from the up
converter board via J2. The ribbon cable pinout is as follows:
• +15 Vdc pin 1.
• -15 Vdc pin 3.
• +8 Vdc pin 5.
• Ground (returns) are pins 2 and 4.
The following ia a list of entries on the UDC interface board status screen.
• +15 Vdc: Input from power supply module
• -15 Vdc: Input from power supply module
• 5 Vdc: Output from 5 volt linear regulator.
• 3.3 Vdc: Output from 3.3 volt linear regulator.
• 8 Vdc: Output from 8 volt switching regulator
4.5.3.2 Exciter Cooling Fan Power
Power for the exciter cooling fan is routed through the UDC interface board as follows
• +15 Volt Float is received at UDC interface board at J4 pin 8, the return is J4 pin 9.