User's Manual
Table Of Contents
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Table of Contents
2604s100TOC.fm
03/08/07 888-2604-001 Page: xi
WARNING: Disconnect primary power prior to servicing.
3.6.3.1 Filter Type. . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.6.3.2 Max Peak Stretch . . . . . . . . . . . . . . . . . . . . . . 3-40
3.6.3.3 RTAC Power On Mode . . . . . . . . . . . . . . . . . . . 3-40
3.6.3.4 RTAC Off Air Mode . . . . . . . . . . . . . . . . . . . . 3-41
3.6.4 Display Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.6.5 External I/O Setup Screen. . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.6.5.1 VSWR Foldback Parameters . . . . . . . . . . . . . . . . 3-43
3.6.5.2 RF Present Cutoff . . . . . . . . . . . . . . . . . . . . . . 3-43
3.6.5.3 External I/O Interface to Transmitter Control Logic . . . . 3-44
3.6.6 Serial I/O Setup Screens . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.6.6.1 Serial Setup Screen 1 of 3, RS-232 . . . . . . . . . . . . . 3-45
3.6.6.2 Serial Setup Screen 2 of 3, Ethernet . . . . . . . . . . . . 3-46
3.6.6.3 Serial Setup Screen 3 of 3, CAN . . . . . . . . . . . . . . 3-47
3.6.7 FPGA Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.6.7.1 FPGA Configure 1/5 . . . . . . . . . . . . . . . . . . . . 3-48
3.6.7.2 FPGA Configure 2/5 . . . . . . . . . . . . . . . . . . . . 3-49
3.6.7.3 FPGA Configure 3/5 . . . . . . . . . . . . . . . . . . . . 3-50
3.6.7.4 FPGA Configure 4/5 . . . . . . . . . . . . . . . . . . . . 3-51
3.6.7.5 FPGA Configure 5/5, Restore Defaults . . . . . . . . . . . 3-52
3.6.8 Change Passwords > Security Setup . . . . . . . . . . . . . . . . . . 3-53
3.6.8.1 User Setup (Locked or Unlocked) . . . . . . . . . . . . . 3-54
3.6.8.2 Diagnostics Setup (Locked or Unlocked). . . . . . . . . . 3-54
3.6.8.3 Factory Setup (Locked or Unlocked) . . . . . . . . . . . . 3-55
3.6.9 Restore Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.7 RTAC Operating Procedures, Main Screen. . . . . . . . . . . . . . . .3-55
3.7.1 From RTAC Section of Main Screen . . . . . . . . . . . . . . . . . . 3-55
3.7.2 From Adaptive Precorrection Board Status Screen . . . . . . . . . . . 3-56
3.7.3 From Down Converter Board Status Screen . . . . . . . . . . . . . . 3-56
3.7.4 From Down Converter Diagnostics Screen . . . . . . . . . . . . . . . 3-56
3.7.5 From RTAC Setup Screen . . . . . . . . . . . . . . . . . . . . . . . 3-57
4 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Transmitter Systems Block Diagram. . . . . . . . . . . . . . . . . . 4-1
4.3 APEX Exciter Digital Assembly Overview . . . . . . . . . . . . . . . 4-2
4.3.1 Controller Board Theory . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2 RTAC and Adaptive Precorrector Board Theory . . . . . . . . . . . . .4-5