User's Manual

APEX™ Exciter Incorporating FLO™ Technology
List of Figures
Page: xvi 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
Figure 3-30 Built In Tests Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
Figure 3-31 System Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
Figure 3-32 Exciter Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35
Figure 3-33 Power Calibration Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-38
Figure 3-34 RTAC Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-38
Figure 3-35 Display Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-41
Figure 3-36 External I/O Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42
Figure 3-37 Serial Setup Screen 1 of 3, RS-232. . . . . . . . . . . . . . . . . . . . . . . . .3-45
Figure 3-38 Serial Setup Screen 2 of 3, Ethernet . . . . . . . . . . . . . . . . . . . . . . . .3-46
Figure 3-39 Serial Setup Screen 3 of 3, CAN . . . . . . . . . . . . . . . . . . . . . . . . . .3-47
Figure 3-40 FPGA Configure 1/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-48
Figure 3-41 FPGA Configure 2/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49
Figure 3-42 FPGA Configure 3/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50
Figure 3-43 FPGA Configure 4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51
Figure 3-44 FPGA Configure 5/5, Restore Defaults . . . . . . . . . . . . . . . . . . . . . .3-52
Figure 3-45 Security Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53
Figure 3-46 System Setup Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54
Figure 4-1 APEX Exciter/ Transmitter - RF Interconnection Block Diagram. . . . . . . . . 4-2
Figure 4-2 APEX Exciter - Signal Flow Block Diagram . . . . . . . . . . . . . . . . . . . 4-4
Figure 4-3 The 44.4 MHz Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-4 Exciter Output Spectral Response, RTAC Bypassed. . . . . . . . . . . . . . . . 4-7
Figure 4-5 Up Converter Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4-6 Analog Assembly Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . .4-10
Figure 4-7 10 MHz Reference Oscillator Block Diagram . . . . . . . . . . . . . . . . . . .4-11
Figure 4-8 Block Diagram First LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
Figure 4-9 Block Diagram Main Phase Lock Loop (2nd LO) . . . . . . . . . . . . . . . . .4-12
Figure 4-10 Output RF Amplifier Block Diagram . . . . . . . . . . . . . . . . . . . . . . .4-13
Figure 5-1 Top View of Exciter (Analog Side) With Cover Removed . . . . . . . . . . . . 5-2
Figure 5-2 Bottom View of Exciter (Digital Side) With Cover Removed. . . . . . . . . . . 5-3
Figure 5-3 APEX Exciter Wiring Diagram, Left Side (see Figure 5-4 for right side) . . . . . 5-4
Figure 5-4 APEX Exciter Wiring Diagram, Right Side (see Figure 5-3 for left side) . . . . . 5-5
Figure 5-5 Frequency Error Troubleshooting Flow Chart . . . . . . . . . . . . . . . . . . .5-12
Figure 5-6 Low or No Output Power Troubleshooting Flow Chart . . . . . . . . . . . . . .5-13
Figure 5-7 Transmitter Fails Mask Test Troubleshooting Flow Chart. . . . . . . . . . . . .5-14
Figure 5-8 Transmitter Has Excessive MER Troubleshooting Flow Chart . . . . . . . . . .5-15
Figure 5-9 Exciter Output Spectral Response, RTAC Bypassed. . . . . . . . . . . . . . . .5-26