User's Manual
Table Of Contents
- Table of Contents
- List of Figures
- List of Tables
- 1 Introduction
- 2 Installation
- 3 Navigating the LCD Display Screens
- 3.1 Basic Operating Procedure
- 3.2 Starting Point: The Main LCD Touch Screen
- 3.3 LCD Display Flow Chart
- 3.4 Details of the Exciter Status Screens
- 3.4.1 System Status Screen
- 3.4.2 Transport Stream Status Screen
- 3.4.3 Adaptive Processing Board Status Screen
- 3.4.4 Digital Processing Screens
- 3.4.4.1 Modulator Board Status, Screen 1/2
- 3.4.4.2 ADC and DAC Boards Status, Screen 2/2
- 3.4.4.3 FLO FPGA Status, Summary, Screen 1/5
- 3.4.4.4 FLO FPGA, GPS & Clock Status, Screen 2/5
- 3.4.4.5 FLO FPGA, Transport Stream Status, Screen 3/5
- 3.4.4.6 FLO FPGA, SFN FIFO Status, Screen 4/5
- 3.4.4.7 FLO FPGA, MTI Status, Screen 5/5
- 3.4.5 IF & RF Processing Status Screens
- 3.4.6 System Control Status Screens
- 3.5 Built In Tests
- 3.6 Details of the System Setup Screens
- 3.7 RTAC Operating Procedures, Main Screen.
- 4 Theory of Operation
- 5 Maintenance and Troubleshooting
- 5.1 Exciter Maintenance
- 5.2 Loading Software
- 5.3 Default Settings For DIagnostics Screens
- 5.4 Typical Settings for the More Critical Exciter Setups
- 5.5 Exciter Troubleshooting Flow Charts
- 5.6 General Troubleshooting
- 5.7 System Troubleshooting
- 5.8 Exciter Troubleshooting
- 6 Parts List
- Appendix A Exciter GUI Screen Captures
APEX™ Exciter Incorporating FLO™ Technology
Navigating the LCD Display Screens Details of the System Setup Screens
Page: 3-50 888-2604-001 03/08/07
WARNING: Disconnect primary power prior to servicing.
3.6.7.3 FPGA Configure 3/5
FPGASetup3.bmp
Figure 3-42 FPGA Configure 3/5
FPGA Configure 3/5 consists of registers whose values are written immediately to the
FPGA when changed through the GUI.
FPGA re-initialization shall occur automatically after any of these registers are changed.
The parameters of the FPGA Configure 3/5 screen are as follows.
• Transmitter Delay: (Time in microseconds – see below for calculations)
• NTWK Geog Delay: (Time in microseconds – see below for calculations)
The value for Transmitter Delay shall be displayed in integer microseconds with a valid
range and the value for the FPGA register value calculated (rounded up to the next integer
value) as shown in the following table:
The value for Network Geographic Delay shall be displayed in integer microseconds with
a valid range and the value for the FPGA register value calculated (rounded up or down to
the next integer value) as shown in the following table:
Bandwidth
Value Range
(in u seconds)
FPGA Register
5 MHz 0 - 221 Value * 37.0
6 MHz 0 - 184 Value * 44.4
7 MHz 0 - 158 Value * 51.8
8 MHz 0 - 137 Value * 59.2
Bandwidth
Value Range
(in u seconds)
FPGA Register
5 MHz -220 - +221 Value * 37.0
6 MHz -183 - +184 Value * 44.4
7 MHz -157 - +158 Value * 51.8
8 MHz -136 - +137 Value * 59.2