User guide

GEL100340
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act
Description
This block performs a bistable timer.
The timer is activated on the rising or on the falling edge of input g in the following way:
l On the rising edge of input g, output o is checked. If output o is FALSE the following operations
are performed:
l Reading the delay time from input t-up.
l Zero setting of the internal variable act (output act).
l Enable of the timer, internal variable ena is set TRUE (output ena).
l After t-up milliseconds are elapsed, during which input g is always TRUE, timer outputs are
set in the following way:
l output o is set TRUE
l output ena is set FALSE
l ouput act keeps the last value reached (t-up value)
l On the falling edge of input g, output o is checked. If output o is TRUE the following operations
are performed:
l Reading the delay time from input t-dw.
l Zero setting of the internal variable act (output act).
l Enable of the timer, internal variable ena is set TRUE (output ena).
l After t-up milliseconds are elapsed, during which input g is always FALSE, timer outputs
are set in the following way:
l output o is set FALSE
l output ena is set FALSE
l ouput act keeps the last value reached (t-up value)
When the timer is active, output ena is TRUE, output act indicates the number of cycles elapsed from start
operations.
When output ena is FALSE, output act could not be significant.
Input t-up and input t-dw are read only in the cycle where a variation is checked, at the rising or falling edge
of input g. Therefore, if input t-up or input t-dw values change while the timer is enabled, output ena is
TRUE, the new value is not considered. This value will be used from the next timer activation.
All times are expressed in milliseconds (ms). Therefore, if input t-up is set to 12, timer output o changes with
12 milliseconds delay and output act changes from 0 to 12.
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