Specifications

Table Of Contents

Cinterion

BGS5 Hardware Interface Overview

2.1 Application Interface

 BGS5_HID_v00.341 2013-09-23

Confidential / Preliminary

Page 18 of 41

2.1.7 I

C Interface

C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It con-

sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts

as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-

tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-

dress, and simple master/slave relationships exist at all times. The module operates as master-

transmitter or as master-receiver. The customer application transmits or receives data only on

request of the module.

The I

C interface can be powered via the V180 line of BGS5. If connected to the V180 line, the

C interface will properly shut down when the module enters the Power Down mode.

Note: Good care should be taken when creating the PCB layout of the host application: The

traces of I2CCLK and I2CDAT should be equal in length and as short as possible.

2.1.8 SPI Interface

Four BGS5 GPIO interface lines can be configured as Serial Peripheral Interface (SPI). The

SPI is a synchronous serial interface for control and data transfer between BGS5 and the ex-

ternal application. Only one application can be connected to the SPI and the interface supports

only master mode. The transmission rates are up to 6.5Mbit/s. The SPI interface comprises the

two data lines MOSI and MISO, the clock line SPI_CLK a well as the chip select line SPI_CS.

The four GPIO lines can be configured as SPI interface signals as follows: GPIO16 --> MOSI,

GPIO17 --> MISO, GPIO18 --> SPI_CLK and GPIO19 --> SPI_CS. The configuration is done

by AT command (see [1]). It is non-volatile and becomes active after a module restart.