Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 Sample Application
- 3 Operating Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
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BGS5 Hardware Interface Overview
2.1 Application Interface
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BGS5_HID_v00.341 2013-09-23
Confidential / Preliminary
Page 19 of 41
2.1.9 TPWM Interfaces
The GPIO6 and GPIO7 interface lines can be configured as Pulse Width Modulation (PWM)
interface lines PWM1 and PWM2. The PWM interface lines can be used, for example, to con-
nect buzzers. The PWM1 line is shared with GPIO7 and the PWM2 line is shared with GPIO6
(for GPIOs see Section 2.1.6). GPIO and PWM functionality are mutually exclusive.
2.1.10 Pulse Counter
The GPIO8 line can be configured as pulse counter line COUNTER. The pulse counter inter-
face can be used, for example, as a clock (for GPIOs see Section 2.1.6).
2.1.11 Control Signals
2.1.11.1 Status LED
The GPIO5 interface line can be configured to drive a status LED that indicates different oper-
ating modes of the module (for GPIOs see Section 2.1.6). GPIO and LED functionality are mu-
tually exclusive.
2.1.11.2 Power Indication Circuit
In Power Down mode the maximum voltage at any digital or analog interface line must not ex-
ceed +0.3V. Exceeding this limit for any length of time might cause permanent damage to the
module.
It is therefore recommended to implement a power indication signal that reports the module’s
power state and shows whether it is active or in Power Down mode. While the module is in
Power Down mode all signals with a high level from an external application need to be set to
low state or high impedance state.
2.1.11.3 Host Wakeup
If no call, data or message transfer is in progress, the host may shut down its own USB inter-
face to save power. If a call or other request (URC’s, messages) arrives, the host can be noti-
fied of these events and be woken up again by a state transition of the ASC0 interface‘s RING0
line.
2.1.11.4 Fast Shutdown
The GPIO4 interface line can be configured as fast shutdown signal line FST_SHDN. The con-
figured FST_SHDN line is an active low control signal and must be applied for at least 10ms.
If unused this line can be left open because of a configured internal pull-up resistor.