Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 Sample Application
- 3 Operating Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
®
BGS5 Hardware Interface Overview
2.3 Sample Application
23
BGS5_HID_v00.341 2013-09-23
Confidential / Preliminary
Page 23 of 41
Figure 6: Schematic diagram of BGS5 sample application
ON
EMERG_RST
VCORE
V180
IGT
RESET
ASC0 (including GPIO1...GPIO3 for
DSR0, DTR0, DCD0 and GPIO24 for
RING0)
ASC1/
GPIO16...GPIO19/
SPI
8
4
CCVCC
CCIO
CCCLK
CCIN
CCRST
SIM
V180
220nF
1nF
I2CCLK
I2CDAT
2.2k
V180
GPIO4 (FST_SHDN)
GPIO5 (Status LED)
GPIO6 (PWM)
GPIO7 (PWM)
GPIO8 (COUNTER)
LED
GND
GND
GND
RF OUT
BATT+
Power supply
Main Antenna
BGS5
All SIM components should be
close to card holder. Keep SIM
wires low capacitive.
*10pF
*10pF
* add optional 10pF for SIM protection
against RF (internal Antenna)
150µF,
Low ESR!
33pF
Blocking**
Blocking**
Blocking**
VDDLP
PWR_IND
BATT+
53
5
GPIO20...GPIO23/
PCM (DAI)
4
Blocking**
VDDLP
100k
100k
100k
4.7k
100k
22k
2.2k
3
USB