User's Manual
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 Sample Application
- 3 Operating Characteristics
- 3.1 Operating Modes
- 3.2 Power Up/Power Down Scenarios
- 3.3 Power Saving
- 3.4 Power Supply
- 3.5 Operating Temperatures
- 3.6 Electrostatic Discharge
- 3.7 Blocking against RF on Interface Lines
- 3.8 Reliability Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
®
ELS61-AUS Hardware Interface Description
3.2 Power Up/Power Down Scenarios
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ELS61-AUS_HID_v00.031 2016-06-03
Confidential / Preliminary
Page 58 of 102
3.2.2.2 Restart ELS61-AUS Using EMERG_RST
The EMERG_RST signal is internally connected to the central baseband processor. A low level
for more than 10ms sets the processor and with it all the other signal pads to their respective
reset state. The reset state is described in Section 3.2.3 as well as in the figures showing the
startup behavior of an interface.
After releasing the EMERG-RST line, i.e., with a change of the signal level from low to high,
the module restarts. The other signals continue from their reset state as if the module was
switched on by the ON signal.
Figure 33: Emergency restart timing
It is recommended to control this EMERG_RST line with an open collector transistor or an open
drain field-effect transistor.
Caution: Use the EMERG_RST line only when, due to serious problems, the software is not
responding for more than 5 seconds. Pulling the EMERG_RST line causes the loss of all infor-
mation stored in the volatile memory. Therefore, this procedure is intended only for use in case
of emergency, e.g. if ELS61-AUS does not respond, if reset or shutdown via AT command fails.
BATT+
ON
EMERG_RST
VCORE
V180
VDDLP
>10ms
System
started
System
started again
Reset
state
Ignition