User's Manual

Cinterion
®
ELS61-AUS Hardware Interface Description
3.2 Power Up/Power Down Scenarios
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ELS61-AUS_HID_v00.031 2016-06-03
Confidential / Preliminary
Page 59 of 102
3.2.3 Signal States after Startup
Table 10 lists the states each interface signal passes through during reset phase and the first
firmware initialization. For further firmware startup initializations the values may differ because
of different GPIO line configurations.
The reset state is reached with the rising edge of the EMERG_RST signal - either after a normal
module startup (see Section 3.2.1.2) or after a reset (see Section 3.2.2.2). After the reset state
has been reached the firmware initialization state begins. The firmware initialization is complet-
ed as soon as the ASC0 interface lines CTS0, DSR0 and RING0 as well as the ASC1 interface
line CTS1 have turned low (see Section 2.1.4 and Section 2.1.5). Now, the module is ready to
receive and transmit data.
Abbreviations used in above Table 10:
Table 10: Signal states
Signal name Reset state First start up configuration
CCIO L O / L
CCRST L O / L
CCCLK L O / L
CCIN T / 100k PD I / 100k PU
RXD0 T / PU O / H
TXD0 T / PD I
CTS0 T / PU O / H
RTS0 T / PU I / PD
GPIO1 T / PD T / PD
GPIO2 T / PD T / PD
GPIO3 T / PD T / PD
GPIO4 T / PD T / PD
GPIO5 T / PD T / PD
GPIO6 T / PD T / PD
GPIO7 T / PD T / PD
GPIO8 T / PD T / PD
GPIO11-GPIO15 T / PD T / PD
GPIO16 T / PD T / PD
GPIO17 T / PD T / PD
GPIO18 T / PD T / PD
GPIO19 T / PD T / PD
GPIO20 T / PD T / PD
GPIO21 T / PD T / PD
GPIO22 T / PD T / PD
GPIO23 T / PD T / PD
GPIO24 T / PD T / PD
I2CCLK T T / OD
I2CDAT T T / OD
L = Low level
H = High level
T = Tristate
I = Input
O = Output
OD = Open Drain
PD = Pull down, 200µA at 1.9V
PU = Pull up, -240µA at 0V