User's Manual

Cinterion
®
ELS61-AUS Hardware Interface Description
Figures
114
 ELS61-AUS_HID_v00.031 2016-06-03
Confidential / Preliminary
Page 7 of 102
Figures
Figure 1: ELS61-AUS system overview ........................................................................ 12
Figure 2: ELS61-AUS block diagram ............................................................................ 13
Figure 3: ELS61-AUS RF section block diagram .......................................................... 14
Figure 4: Numbering plan for connecting pads (bottom view)....................................... 15
Figure 5: USB circuit ..................................................................................................... 23
Figure 6: Serial interface ASC0..................................................................................... 25
Figure 7: ASC0 startup behavior................................................................................... 26
Figure 8: Serial interface ASC1..................................................................................... 27
Figure 9: ASC1 startup behavior................................................................................... 28
Figure 10: External UICC/SIM/USIM card holder circuit ................................................. 30
Figure 11: SIM interface - enhanced ESD protection...................................................... 31
Figure 12: RTC supply variants....................................................................................... 32
Figure 13: GPIO startup behavior ................................................................................... 34
Figure 14: I
2
C interface connected to V180 .................................................................... 35
Figure 15: I
2
C startup behavior ....................................................................................... 36
Figure 16: Characteristics of SPI modes......................................................................... 37
Figure 17: Status signaling with LED driver .................................................................... 38
Figure 18: Power indication circuit .................................................................................. 39
Figure 19: Fast shutdown timing ..................................................................................... 40
Figure 20: Antenna pads (bottom view) .......................................................................... 43
Figure 21: Embedded Stripline with 65µm prepreg (1080) and 710µm core .................. 44
Figure 22: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 ................ 45
Figure 23: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2............................ 46
Figure 24: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1............................ 47
Figure 25: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2............................ 48
Figure 26: Routing to application‘s RF connector - top view........................................... 49
Figure 27: Schematic diagram of ELS61-AUS sample application ................................. 51
Figure 28: Sample level conversion circuit...................................................................... 52
Figure 29: Sample circuit for applying power using an external µC ................................ 55
Figure 30: Sample circuit for applying power using an external voltage supervisory
circuit.............................................................................................................. 55
Figure 31: ON circuit options........................................................................................... 56
Figure 32: ON timing ....................................................................................................... 57
Figure 33: Emergency restart timing ............................................................................... 58
Figure 34: Switch off behavior......................................................................................... 60
Figure 35: Power saving and paging in WCDMA networks............................................. 63
Figure 36: Power saving and paging in LTE networks.................................................... 64
Figure 37: Wake-up via RTS0......................................................................................... 65
Figure 38: Position of reference points BATT+ and GND ............................................... 68
Figure 39: ESD protection for RF antenna interface ....................................................... 70
Figure 40: EMI circuits..................................................................................................... 71
Figure 41: ELS61-AUS– top and bottom view................................................................. 74
Figure 42: Dimensions of ELS61-AUS (all dimensions in mm) ....................................... 75
Figure 43: Land pattern (top view) .................................................................................. 76
Figure 44: Recommended design for 110µm micron thick stencil (top view).................. 77
Figure 45: Recommended design for 150µm micron thick stencil (top view).................. 77
Figure 46: Reflow Profile................................................................................................. 79
Figure 47: Carrier tape .................................................................................................... 83
Figure 48: Reel direction ................................................................................................. 83
Figure 49: Barcode label on tape reel ............................................................................. 84