User's Manual

Table Of Contents

Cinterion

ELS61-US Hardware Interface Overview

2.2 SPI Interface

 ELS61-US_HIO_v00.281 2016-02-11

Confidential / Preliminary

Page 16 of 40

2.1.6 I

C Interface

C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It con-

sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts

as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-

tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-

dress, and simple master/slave relationships exist at all times. The module operates as master-

transmitter or as master-receiver. The customer application transmits or receives data only on

request of the module.

The I

C interface can be powered via the V180 line of ELS61-US. If connected to the V180 line,

the I

C interface will properly shut down when the module enters the Power Down mode.

Note: Good care should be taken when creating the PCB layout of the host application: The

traces of I2CCLK and I2CDAT should be equal in length and as short as possible.

2.2 SPI Interface

Four ELS61-US GPIO interface lines can be configured as Serial Peripheral Interface (SPI).

The SPI is a synchronous serial interface for control and data transfer between ELS61-US and

the external application. Only one application can be connected to the SPI and the interface

supports only master mode. The transmission rates are up to 6.5Mbit/s. The SPI interface com-

prises the two data lines MOSI and MISO, the clock line SPI_CLK a well as the chip select line

SPI_CS.