User's Manual
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Quick reference data
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Limiting values
- 8. Recommended operating conditions
- 9. Thermal characteristics
- 10. Characteristics
- 10.1 Power management characteristics
- 10.2 Antenna presence self test thresholds
- 10.3 Typical 27.12 MHz Crystal requirements
- 10.4 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)
- 10.5 RSTPD_N input pin characteristics
- 10.6 Input pin characteristics for I0, I1 and TESTEN
- 10.7 RSTOUT_N output pin characteristics
- 10.8 Input/output characteristics for pin P70_IRQ
- 10.9 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1
- 10.10 Input/output pin characteristics for P35
- 10.11 Input/output pin characteristics for DP and DM
- 10.12 Input pin characteristics for SCL
- 10.13 Input/output pin characteristics for SDA
- 10.14 Output pin characteristics for DELATT
- 10.15 Input pin characteristics for SIGIN
- 10.16 Output pin characteristics for SIGOUT
- 10.17 Input/output pin characteristics for P34
- 10.18 Output pin characteristics for LOADMOD
- 10.19 Input pin characteristics for RX
- 10.20 Output pin characteristics for AUX1/AUX2
- 10.21 Output pin characteristics for TX1/TX2
- 10.22 System reset timing
- 10.23 Timing for the I2C-bus interface
- 10.24 Temperature sensor
- 11. Application information
- 12. Abbreviations
- 13. Revision history
- 14. Legal information
- 15. Contact information
- 16. Tables
- 17. Figures
- 18. Contents
PR533_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.6 — 27 October 2014
206436 25 of 36
NXP Semiconductors
PR533
USB NFC integrated reader solution
10.21 Output pin characteristics for TX1/TX2
Table 32. Output pin characteristics for TX1/TX2
Symbol Parameter Conditions Min Typ Max Unit
V
OH
HIGH-level output voltage V
DD(TVDD)
= 3 V;
I
O
= 32 mA; CWGsN = Fh
- - 150 mV
V
DD(TVDD)
= 3 V;
I
O
= 80 mA; CWGsN = Fh
- - 400 mV
V
OL
LOW-level output voltage V
DD(TVDD)
= 2.5 V;
I
O
= 32 mA; CWGsN = Fh
- - 240 mV
V
DD(TVDD)
= 2.5 V;
I
O
= 80 mA; CWGsN = Fh
- - 640 mV
Table 33. Output resistance for TX1/TX2
Symbol Parameter Conditions1 CWGsP Min Typ Max Unit
R
OH
HIGH-level out-
put resistance
V
DD(TVDD)
= 3 V; V
O
=
V
DD(TVDD)
100 mV
01h 133 180 251
02h 67 90 125
04h 34 46 62
08h 17 23 31
10h 8.5 12 15.5
20h 4.7 6 7.8
3Fh 2.3 3 4.4
R
OL
LOW-level output
resistance
10h 34 46 62
20h 17 23 31
40h 8.5 12 15.5
80h 4.7 6 7.8
F0h 2.3 3 4.4