Owner's Manual

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>>>>> Channel A/B
Channel A/B Timing Settings
CMOS Setup Utility-Copyright (C) 1984-2011 Award Software
Channel A/B Timing Settings

: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Item Help
Menu Level

x Static tRead Value Auto
x tRD Phase0 Adjustment Auto
x tRD Phase1 Adjustment Auto
x tRD Phase2 Adjustment Auto
x tRD Phase3 Adjustment Auto
x Trd2rd(Different Rank) Auto
x Twr2wr(Different Rank) Auto
x Twr2rd(Different Rank) Auto
x Trd2wr(Same/Diff Rank) Auto
x DIMM1 Clock Skew Control Auto
x DIMM2 Clock Skew Control Auto
x DDR Write Leveling Auto
x DDR Write Training Auto
Static tRead Value
Options are: Auto (default), 1~15.
tRD Phase0 Adjustment
Options are: Auto (default), 0-Normal, 1-Advanced.
tRD Phase1 Adjustment
Options are: Auto (default), 0-Normal, 1-Advanced.
tRD Phase2 Adjustment
Options are: Auto (default), 0-Normal, 1-Advanced.
tRD Phase3 Adjustment
Options are: Auto (default), 0-Normal, 1-Advanced.
Trd2rd(Different Rank)
Options are: Auto (default), 1~15.
Twr2wr(Different Rank)
Options are: Auto (default), 1~15.
Twr2rd(Different Rank)
Options are: Auto (default), 1~15.
Trd2wr(Same/Diff Rank)
Options are: Auto (default), 1~15.
DIMM1 Clock Skew Control
Options are: Auto (default), +800ps~-700ps.
DIMM2 Clock Skew Control
Options are: Auto (default), +800ps~-700ps.
DDR Write Leveling
Allows you to determine whether to ne-tune memory parameters to enhance memory compatibility.
Auto Lets the BIOS decide whether to enable this function. (Default)
Disabled Disables this function.
Enabled Enables this function to enhance memory compatibility.