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Data Sheet

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512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

GLS27SF512 / GLS27SF010 / GLS27SF020

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8

• 4.5-5.5V Read Operation

• Superior Reliability

– Endurance: At least 1000 Cycles

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Read Access Time

– 70 ns

• Fast Byte-Program Operation

– Byte-Program Time: 20 µs (typical)

– Chip Program Time:

1.4 seconds (typical) for GLS27SF512

2.8 seconds (typical) for GLS27SF010

5.6 seconds (typical) for GLS27SF020

• Electrical Erase Using Programmer

– Does not require UV source

– Chip-Erase Time: 100 ms (typical)

• TTL I/O Compatibility

• JEDEC Standard Byte-wide EPROM Pinouts

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP for GLS27SF010/020

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The GLS27SF512/010/020 are a 64K x8 / 128K x8 / 256K

x8 CMOS, Many-Time Programmable (MTP) low cost

flash, manufactured with high performance SuperFlash

technology. The split-gate cell design and thick oxide tun-

neling injector attain better reliability and manufacturability

compared with alternate approaches. These MTP devices

can be electrically erased and programmed at least 1000

times using an external programmer with a 12V power sup-

ply. They have to be erased prior to programming. These

devices conform to JEDEC standard pinouts for byte-wide

memories.

Featuring high-performance Byte-Program, the

GLS27SF512/010/020 provide a Byte-Program time of 20

µs. Designed, manufactured, and tested for a wide spec-

trum of applications, these devices are offered with an

endurance of at least 1000 cycles. Data retention is rated at

greater than 100 years.

The GLS27SF512/010/020 are suited for applications that

require infrequent writes and low power nonvolatile stor-

age. These devices will improve flexibility, efficiency, and

performance while matching the low cost in nonvolatile

applications that currently use UV-EPROMs, OTPs, and

mask ROMs.

To meet surface mount and conventional through hole

requirements, the GLS27SF512 are offered in 32-lead

PLCC, 32-lead TSOP, and 28-pin PDIP packages. The

GLS27SF010/020 are offered in 32-pin PDIP, 32-lead

PLCC, and 32-lead TSOP packages. See Figures 3, 4,

and 5 for pin assignments.

Device Operation

The GLS27SF512/010/020 are a low cost flash solution

that can be used to replace existing UV-EPROM, OTP,

and mask ROM sockets. These devices are functionally

(read and program) and pin compatible with industry

standard EPROM products. In addition to EPROM func-

tionality, these devices also support electrical Erase

operation via an external programmer. They do not

require a UV source to erase, and therefore the pack-

ages do not have a window.

Read

The Read operation of the GLS27SF512/010/020 is con-

trolled by CE# and OE#. Both CE# and OE# have to be

low for the system to obtain data from the outputs. Once

the address is stable, the address access time is equal to

the delay from CE# to output (T

). Data is available at the

output after a delay of T

from the falling edge of OE#,

assuming that CE# pin has been low and the addresses

GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories

Summary of content (23 pages)

PAGE 1
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories Data Sheet FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 • 4.5-5.
PAGE 2
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Product Identification Mode have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
PAGE 3
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet SuperFlash Memory X-Decoder A15 - A0 Address Buffer Y-Decoder CE# OE#/VPP A9 Control Logic I/O Buffers DQ7 - DQ0 1152 B2.1 FIGURE 1: Functional Block Diagram - GLS27SF512 SuperFlash Memory X-Decoder AMS - A0 Address Buffer Y-Decoder CE# OE# A9 I/O Buffers Control Logic VPP DQ7 - DQ0 PGM# AMS = A17 for GLS27SF020, A16 for GLS27SF010 1152 B3.
PAGE 4
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 GLS27SF010/020 NC A13 A17 PGM# PGM# A14 VDD VDD VDD VPP VPP NC A16 A15 A16 A12 A15 A15 GLS27SF512 A12 GLS27SF010 A7 GLS27SF020 A12 Data Sheet GLS27SF512 GLS27SF512 4 3 2 1 32 31 30 GLS27SF010/020 A7 A6 5 29 A8 A14 A6 A5 6 28 A9 A13 A5 A4 7 27 A11 A8 A4 A3 8 26 NC A9 A3 A2 9 25 A11 A2 A1 10 24 OE#/VPP A10 A1 A0 11 23 CE# A10 A0 NC 12 22 DQ7 CE#
PAGE 5
12 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet GLS27SF020 GLS27SF010 GLS27SF512 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS GLS27SF512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin PDIP Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS GLS27SF010 GLS27SF020 1 2 3 4 5 32-pin 6 PD
PAGE 6
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet TABLE 3: Operation Modes Selection for GLS27SF512 Mode CE# OE#/VPP A9 DQ Read Output Disable Address VIL VIL AIN DOUT AIN VIL VIH X1 High Z X Program VIL VPPH AIN DIN AIN Standby VIH X X High Z X Chip-Erase VIL VPPH VH High Z X Program/Erase Inhibit VIH VPPH X High Z X Product Identification VIL VIL VH Manufacturer’s ID (BFH) Device ID (A4H) A15-A1=VIL, A0=VIL
PAGE 7
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
PAGE 8
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet TABLE 6: Program/Erase DC Operating Characteristics for GLS27SF512 VDD=4.5-5.5V, VPP=VPPH (TA=25°C±5°C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max IPP VPP Erase or Program Current 3 mA CE#=VIL, OE#/VPP=11.
PAGE 9
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet AC CHARACTERISTICS TABLE 11: Read Cycle Timing Parameters VDD = 4.5-5.
PAGE 10
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet TABLE 13: Program/Erase Cycle Timing Parameters for GLS27SF010/020 Symbol TCES TCEH TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A
PAGE 11
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet TAA TRC ADDRESS TCE CE# TOE OE# TOLZ TOH TOHZ TCHZ DQ7-0 HIGH-Z DATA VALID DATA VALID TCLZ 1152 F03.0 FIGURE 6: Read Cycle Timing Diagram for GLS27SF512/010/020 ADDRESS (EXCEPT A9) CE# TEW DQ7-0 OE#/VPP VDD VSS VPPH TVPH TVPS VPPH TPRT TVR TVR TA9S A9 VIH VIL TART TA9H 1152 F04b.1 FIGURE 7: Chip-Erase Timing Diagram for GLS27SF512 ©2010 Greenliant Systems, Ltd.
PAGE 12
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet ADDRESS (EXCEPT A9) TCEH CE# OE# VIH DQ7-0 TVPS VPPH VPP VDD VSS TPRT VPPH A9 TVPH TVR TA9S VIH VIL TART TA9H TEW PGM# TCES 1152 F04c.1 FIGURE 8: Chip-Erase Timing Diagram for GLS27SF010/020 ADDRESS VALID ADDRESS TAH TAS TPW CE# TDS DQ7-0 HIGH-Z TDH DATA VALID TVR TVPS VPPH OE#/VPP VDD VSS TVPH TPRT 1152 F05b.
PAGE 13
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet ADDRESS ADDRESS VALID TAH TAS CE# TCEH OE# VIH TDH TDS DQ7-0 HIGH-Z DATA VALID TVPS VPPH VPP VDD VSS TPW TVPH TPRT PGM# 1152 F05c.1 TCES FIGURE 10: Byte-Program Timing Diagram for GLS27SF010/020 ©2010 Greenliant Systems, Ltd.
PAGE 14
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 1152 F06.0 AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10%  90%) are <10 ns.
PAGE 15
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Start A9 = VH OE#/VPP = VPPH Erase 100ms pulse (CE# = VIL) OE#/VPP = VDD or VSS A9 = VIL or VIH Wait for OE#/VPP and A9 Recovery Time Read Device (CE# = OE# = VIL) No Compare All bytes to FFH Yes Device Passed Device Failed 1152 F08b.2 FIGURE 13: Chip-Erase Algorithm for GLS27SF512 ©2010 Greenliant Systems, Ltd.
PAGE 16
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Start A9 = VH, VPP = VPPH CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL) PGM# = VIH A9 = VIL or VIH Wait A9 Recovery Time Read Device No Compare all bytes to FFH Yes Device Passed Device Failed 1152 F08c.1 FIGURE 14: Chip-Erase Algorithm for GLS27SF010/020 ©2010 Greenliant Systems, Ltd.
PAGE 17
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Start Erase* OE#/VPP = VPPH Address = First Location Program 20µs pulse (CE# = VIL) Increment Address OE#/VPP = VDD or VSS Last Address? No Yes Wait for OE#/VPP RecoveryTime Read Device (CE# = OE# = VIL) Compare all bytes to original data No Yes Device Passed Device Failed 1152 F09b.2 * See Figure 13 FIGURE 15: Byte-Program Algorithm for GLS27SF512 ©2010 Greenliant Systems, Ltd.
PAGE 18
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet Start Erase* VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 20µs pulse (PGM# = VIL) Increment Address Last Address? No Yes Read Device Compare all bytes to original data No Yes Device Passed Device Failed 1152 F09c.1 * See Figure 14 FIGURE 16: Byte-Program Algorithm for GLS27SF010/020 ©2010 Greenliant Systems, Ltd.
PAGE 19
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet PRODUCT ORDERING INFORMATION GLS 27 XX SF 020 XX XXXX - 70 - XXX - 3C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C Minimum Endurance 3 = 1,000 cycles Read Access Speed 70 = 70 ns Device Density - x8 Organization 020 = 2 Mbit 010 = 1 Mbit
PAGE 20
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30˚ .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1.
PAGE 21
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.
PAGE 22
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet 32 CL 1 Pin #1 Identifier 1.655 1.645 .075 .065 7˚ 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0˚ 15˚ .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3.
PAGE 23
512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash GLS27SF512 / GLS27SF010 / GLS27SF020 Data Sheet TABLE 14: Revision History Number Description Date 02 • 2002 Data Book Feb 2002 03 • Document Control Release (SST Internal): No technical changes Apr 2002 04 • Corrected IH Supervoltage Current for A9 from 100 µA to 200 µA in Tables 5, 6, and 7 Jul 2002 05 • Corrected the Test Conditions for IDD and IPPR in Table 5 on page 7 Sep 2003 06 • • Corrected the Max value for IPP from 1 mA t