FM17520 Contactless Transceiver IC Datasheet Oct.2016 FM17520 Contactless Transceiver IC Ver 1.
INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION; THEY DO NOT CONVEY ANY LICENSE UNDER ANY INTELLECTUAL PROPERTY RIGHTS, OR ANY OTHER RIGHTS, BELONGING TO SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD OR A THIRD PARTY.
Contents Contents CONTENTS ............................................................................................................................................................................. 3 TABLES ................................................................................................................................................................................... 5 FIGURES ...............................................................................................................
Contents 10.2 HARD POWER DOWN ..................................................................................................................................................... 53 10.2.1 Data Retention in HPD Mode ................................................................................................................................. 53 10.3 SOFT POWER DOWN..............................................................................................................................................
Tables Tables TAB1-1 TAB2-1 TAB3-1 TAB3-2 TAB3-3 TAB3-4 TAB3-5 TAB3-6 TAB3-7 TAB3-8 TAB3-9 TAB3-10 TAB3-11 TAB3-12 TAB3-13 TAB3-14 TAB3-15 TAB3-16 TAB3-17 TAB3-18 TAB3-19 TAB3-20 TAB3-21 TAB3-22 TAB3-23 TAB3-24 TAB3-25 TAB3-26 TAB3-27 TAB3-28 TAB3-29 TAB3-30 TAB3-31 TAB3-32 TAB3-33 TAB3-34 TAB3-35 TAB3-36 TAB3-37 TAB3-38 TAB3-39 TAB3-40 TAB3-41 TAB3-42 TAB3-43 TAB3-44 TAB3-45 TAB3-46 TAB3-47 TAB3-48 TAB3-49 TAB3-50 TAB3-51 TAB3-52 FM17520 QFN32 PIN DESCRIPTION .............................................
Tables TAB3-53 TAB3-54 TAB3-55 TAB3-56 TAB3-57 TAB3-58 TAB3-59 TAB3-60 TAB3-61 TAB3-62 TAB3-63 TAB3-64 TAB3-65 TAB3-66 TAB3-67 TAB3-68 TAB3-69 TAB3-70 TAB3-71 TAB3-72 TAB3-73 TAB3-74 TAB3-75 TAB3-76 TAB3-77 TAB3-78 TAB3-79 TAB3-80 TAB3-81 TAB3-82 TAB3-83 TAB3-84 TAB3-85 TAB3-86 TAB3-87 TAB3-88 TAB3-89 TAB3-90 TAB3-91 TAB3-92 TAB3-93 TAB3-94 TAB3-95 TAB3-96 TAB3-97 TAB3-98 TAB3-99 TAB3-100 TAB3-101 TAB3-102 TAB3-103 TAB3-104 TAB3-105 TAB3-106 TAB3-107 TAB3-108 TAB3-109 TAB3-110 RXTHRESHOLDREG BITS DESCRIPTI
Tables TAB3-111 TAB3-112 TAB3-113 TAB3-114 TAB3-115 TAB3-116 TAB3-117 TAB3-118 TAB3-119 TAB3-120 TAB3-121 TAB3-122 TAB3-123 TAB3-124 TAB3-125 TAB3-126 TAB3-127 TAB3-128 TAB3-129 TAB3-130 TAB3-131 TAB3-132 TAB3-133 TAB3-134 TAB3-135 TAB3-136 TAB3-137 TAB4-1 TAB4-2 TAB4-3 TAB4-4 TAB5-1 TAB5-2 TAB6-1 TAB8-1 TAB10-1 TAB14-1 TAB15-1 TAB15-2 TAB15-3 TAB15-4 TAB15-5 TAB15-6 TAB15-7 TAB17-1 TAB17-2 TAB17-3 TESTBUSREG BITS DESCRIPTION .................................................................................
Figures Figures FIG1-1 FIG1-2 FIG2-1 FIG2-2 FIG2-3 FIG4-1 FIG4-2 FIG5-1 FIG12-1 FIG13-1 FIG16-1 FIG17-1 FIG19-1 FM17520 BLOCK DIAGRAM ................................................................................................................................................. 10 FM17520 QFN32 PINNING ASSIGNMENT (TOP VIEW) .............................................................................................................. 11 FM17520 APPLICATION DIAGRAM .........................................
1 Product Overview 1 Product Overview 1.1 Introduction The FM17520 is a highly integrated transceiver IC for contactless communication at 13.56 MHz, supporting Reader/Writer mode of ISO/IEC 14443A. The FM17520’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC14443A cards and transponders without additional active circuitry.
1 Product Overview 1.3 Block Diagram Control Register Bank Host Interface control Control Engine FIFO codec Receiver Transmitter Fig1-1 FM17520 Contactless Transceiver IC Encryption Unit CRC co-processor Interrupt control clock/reset control Programable timer Power Manage Unit FM17520 block diagram Ver 1.
RX AVSS AUX1 AUX2 FM17520 Pinning Assignment OSCIN 1.4.1 IRQ Pinning Information NSS 1.
1 Product Overview Pin Symbol Type Description clock(27.12MHz) 22 23 24 25 26 27 28 29 30 31 32 OSCOUT IRQ NSS D1 D2 D3 D4 SCK MOSI MISO NC FM17520 Contactless Transceiver IC O crystal oscillator output O interrupt request output, indicates an interrupt event I SPI interface enable IO test port IO test port IO test port IO test port I SPI serial clock input I SPI master output and slave input O SPI master input and slave output Tab1-1 FM17520 QFN32 pin description Ver 1.
2 Functional Description 2 Functional Description 2.1 General Description FM17520 Reader IC supports ISO/IEC14443 A protocols using various transfer speeds. Battery FM17522 CARD MCU PICC PCD Fig2-1 2.2 FM17520 application diagram ISO/IEC14443 A Functionality Tab 2-1 lists the transfer speeds of ISO/IEC14443A supported by FM17520.
2 Functional Description Fig2-3 PICC standard frames The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg register’s ParityDisable bit. FM17520 Contactless Transceiver IC Ver 1.
3 FM17520 Register Set 3 FM17520 Register Set 3.1 FM17520 Registers Overview 3.1.
3 FM17520 Register Set Page 2 Addr Register Name E F 0 1 2 3 4 5 6 RFU RFU RFU 3 Shows the actual result of the CRC calculation RFU ModWidthReg RFU RFCfgReg Reserved for future use Controls the setting of the ModWidth Reserved for future use Configures the receiver gain Selects the conductance of the antenna driver pins TX1 and TX2 Selects the conductance of the antenna driver pins TX1 and TX2 Selects the conductance of the antenna driver pins TX1 and TX2 GsNReg 8 CWGsPReg 9 ModGsPReg A B C D
3 FM17520 Register Set 3.1.2 Register Bit Behavior The table belowdescribles the behavior and the access conditions of registers. Abbre Behavior Description viation These bits can be written and read by theμ-Controller. Since theyare read and r/w used only for control means, their content is not influenced byinternal state write machines. These bits can be written and read by theμ-Controller, and they may also dy dynamic be written by internalstate machines.
3 FM17520 Register Set Bit Symbol 3-0 3.2.1.3 Description Command ready for operations. Remark: The bit Power Down cannot be set, when the command SoftReset has been activated. Command register. Activates a command according to the Command Code. Reading it shows, which command is actually executed Tab3-7 CommandReg bits description CommIEnReg_address 02h Control bits to enable and disable the passing of interrupt requests.
3 FM17520 Register Set 3.2.1.5 Bit Symbol 7 IRQPushPull 6-5 4 3 TinActIEn RFU 2 CRCIEn 1-0 RFU Description Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. Reserved for future use. Allows the TIN active interrupt request to be propagated to pin IRQ. Reserved for future use. Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. Reserved for future use.
3 FM17520 Register Set 3.2.1.6 DivIRqReg_address05h Contain Interrupt Request bits. Bit 7 6 5 Definitio Set2 RFU RFU n Access w Rights Reset 0 0 0 Value 4 3 2 1 0 TinActIRq RFU CRCIRq RFU RFU dy - dy - - x 0 0 x x Tab3-14 DivIRqReg register 3.2.1.7 Bit Symbol 7 Set2 6-5 - 4 TinActIRq 3 - 2 CRCIRq 1-0 - Description Set to logic 1, Set2 defines thatthe marked bits in the register DivIRqReg are set.
3 FM17520 Register Set 3.2.1.8 Bit Symbol 4 BufferOvfl 3 CollErr 2 CRCErr 1 ParityErr 0 ProtocolErr Description Set to logic 1, if the host controller or a FM17520’s internal state machine (e.g. receiver) tries to write datainto the FIFO-bufferalthough the FIFO-buffer is already full. Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit/s.
3 FM17520 Register Set 3.2.1.9 Bit Symbol 0 LoAlert Description Set to logic 1, when the numberof bytes stored in the FIFO-buffer fulfills the following equation: LoAlert = FIFOLength ≤ WaterLevel Example： FIFOLength = 4, WaterLevel = 4 LoAlert = 1 FIFOLength = 5, WaterLevel = 4 LoAlert = 0 Tab3-19 Status1Reg bits description Status2Reg_address 08h Contain status bits of the Receiver, Transmitter and Data mode detector.
3 FM17520 Register Set 3.2.1.10 FIFODataReg_address 09h Input and output port of 64 byte FIFO buffer. Bit 7 6 5 Definition Access Rights Reset Value 4 3 2 1 0 FIFOData dy dy dy dy dy dy dy dy x x x x x x x x Tab3-22 FIFODataReg register 3.2.1.11 Bit Symbol 7-0 FIFOData Description Data input and output port for the internal 64 byte FIFO buffer. The FIFO buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs.
3 FM17520 Register Set Bit 3.2.1.13 Symbol Description number of bytes in the FIFO buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Tab3-27 WaterLevelReg bits description ControlReg_address 0Ch Some control bits.
3 FM17520 Register Set 3.2.1.15 Bit Symbol 2-0 TxLastBits Description Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted. Tab3-31 BitFramingReg bits description CollReg_address 0Eh Define the first bit collision detected on the RF interface. Bit 7 6 Definition Access Rights Reset Value 3.2.1.
3 FM17520 Register Set 3.2.2 Page 1：Communication 3.2.2.1 RFU_address 10h Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value RFU RFU RFU RFU RFU RFU RFU RFU - - - - - - - - 0 0 0 0 0 0 0 0 Tab3-36 RFU register 3.2.2.2 Bit Symbol 7-0 RFU Description Reserved for future use. Tab3-37 RFUReg bits description ModeReg_address 11h Define general mode settings for transmitting and receiving.
3 FM17520 Register Set 3.2.2.3 TxModeReg_address 12h Define the data rate and framing during transmission. Bit 7 6 5 Definition Access Rights Reset Value 3.2.2.4 3 2 1 0 InvMod RFU RFU RFU r/w - - - 0 0 0 0 Tab3-40 TxModeReg register 0 0 0 TxCRCEn TxSpeed r/w dy 0 Bit Symbol 7 TxCRCEn 6-4 TxSpeed 3 2-0 InvMod RFU 4 dy dy Description Set to logic 1, this bit enables the CRC generation during data transmission. Remark: This bit shall only be set to logic 0 at 106 kbit/s.
3 FM17520 Register Set 3.2.2.5 Bit Symbol 3 RxNoErr 2 RxMultiple 1-0 RFU Description If set to logic 1 a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the Receive and Transceive commands will not terminate automatically.
3 FM17520 Register Set Bit on Access Rights Reset Value 7 6 ASK 5 4 3 2 1 0 - r/w - - - - - - 0 0 0 0 0 0 0 0 Tab3-46 TxASKReg register Bit Symbol 7 RFU 6 5-0 3.2.2.7 Description Reserved for future use. Set to logic 1, Force100ASK forces a 100% ASK modulation Force100ASK independent of the setting in register ModGsPReg. RFU Reserved for future use. Tab3-47 TxASKReg bits description TxSelReg_address 16h Select the sources for the antenna driver.
3 FM17520 Register Set 3.2.2.8 RxSelReg_address 17h Select internal receiver settings. Bit 7 Definition Access Rights Reset Value Bit 3.2.2.
3 FM17520 Register Set 3.2.2.11 Bit Symbol 7-6 AddIQ 5 FixIQ 4 - 3-2 TauRcv 1-0 TauSync Description Defines the use of I and Q channel during reception. Remark: FixIQ has to be set to logic 0 to enable the following settings. Value Description 00 Select the stronger channel Select the stronger and freeze the selected during 01 communication 10 combines the I and Q channel 11 Reserved If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to I channel.
3 FM17520 Register Set 3.2.2.13 TxReg_address 1Ch Control part of transmission parameters in ISO/IEC 14443A. Bit 7 6 5 4 Definition Access Rights Reset Value 3.2.2.14 RFU 0 Bit Symbol 7-2 RFU 1-0 TxWait RFU 1 3 2 RFU RFU RFU 1 0 0 Tab3-60 TxReg register 1 RFU 0 0 TxWait r/w r/w 1 0 Description Reserved for future use. These bits define the additional response time. Per default 7 bits are added to the value of the register bit.
3 FM17520 Register Set Bit Symbol 7-0 RFU Description Reserved for future use. Tab3-67 RFUReg bits description 3.2.3 Page 2：Configuration 3.2.3.1 RFU_address 20h Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value RFU RFU RFU RFU RFU RFU RFU RFU - - - - - - - - 0 0 0 0 0 0 0 0 Tab3-68 RFU register 3.2.3.2 Bit Symbol 7-0 RFU Description Reserved for future use.
3 FM17520 Register Set Bit Access Rights Reset Value 7 6 5 4 3 2 1 0 - - - - - - - - 0 0 0 0 0 0 0 0 Tab3-74 RFU register 3.2.3.5 Bit Symbol 7-0 RFU Description Reserved for future use. Tab3-75 RFUReg bits description ModWidthReg_address24h Control the modulation width settings. Bit 7 Definition Access Rights Reset Value 3.2.3.
3 FM17520 Register Set Bit 3-0 3.2.3.8 Symbol Description 000 18 dB 001 23 dB 010 18 dB 011 23 dB 100 33 dB 101 38 dB 110 43 dB 111 48 dB Reserved for future use. Tab3-81 RFCfgReg bits description RFU GsNReg_address 27h Select the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Bit 7 6 5 4 3 2 1 0 Definition Access Rights Reset Value 3.2.3.
3 FM17520 Register Set 3.2.3.10 ModGsPReg_address 29h Define the driver P-output conductance during modulation. Bit 7 6 5 4 Definition Access Rights Reset Value 3.2.3.11 RFU 0 3 2 RFU ModGsP r/w r/w r/w r/w 0 1 0 0 0 Tab3-86 ModGsPReg register 1 0 r/w 0 r/w 0 Bit Symbol Description 7-6 - 5-0 ModGsP Reserved for future use. The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index.
3 FM17520 Register Set Bit 3.2.3.12 Symbol TPrescalerLoReg_address 2Bh Bit 7 Definition Access Rights Reset Value r/w 0 Bit 6 5 2 1 0 r/w 0 r/w 0 r/w 0 Description Defines lower 8 bits for TPrescaler. TPrescaler_Lo The fTimer formula refers to the description of Tprescaler_Hi in TmodeReg register.
3 FM17520 Register Set Bit Symbol 7-0 3.2.3.16 Description TCounterVal_Hi Current value of the timer, higher 8 bits. Tab3-97 TCounterValHiReg bits description TcounterValLoReg_address 2Fh Bit 7 Definition Access Rights Reset Value r x Bit 7-0 6 5 4 TCounterVal_Lo r r r r x x x x Tab3-98 TCounterValLoReg register Symbol Page 3：Test 3.2.4.
3 FM17520 Register Set Bit 7 6 Reset Value 0 0 Tab3-104 Bit 7 6 5 4-0 3.2.4.4 4 3 2 1 0 0 0 0 TestSel2Reg register 0 0 0 Symbol Description If set to logic 1, the testbus is mapped to the parallel port by the following order: TstBusFlip TstBusBit2, TstBusBit6, TstBusBit5, TstBusBit0. Refer to section 14 “Testsignals”. Starts and enables the PRBS9 sequence according ITU-TO150. Remark: All relevant registers to transmit data have to be PRBS9 configured before entering PRBS9 mode.
3 FM17520 Register Set Bit 6-5 4-1 0 3.2.4.6 Symbol Description TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal. RFU Reserved for future use. Defines the value of the 4-bit parallel port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. TestPinValue Remark: Reading the register indicates the actual status of the pins D4~D1 if UseIO is set to logic 1.
3 FM17520 Register Set 3.2.4.9 Bit Symbol 7-0 RFT Description Reserved for production tests. Tab3-115 RFTReg bits description AnologTestReg_address 38h Control the pins AUX1 and AUX2. Bit 7 6 Definition Access Rights Reset Value r/w 0 Bit Symbol 7-4 AnalogSelAux1 5 4 3 2 1 0 AnalogSelAux1 AnalogSelAux2 r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 Tab3-116 AnologTestReg register r/w 0 Description Controls the AUX pin. Remark: All test signals are described in section 15 “Testsignals”.
3 FM17520 Register Set Bit Symbol Description Defines the testvalue for TestDAC1. The output of the DAC1 can be TestDAC1 switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg. Tab3-119 TestDAC1Reg bits description 5-0 3.2.4.11 TestDAC2Reg_address 3Ah Define the testvalue for TestDAC2.
3 FM17520 Register Set 3.2.4.14 3.2.4.15 3.2.4.16 3.2.5 RFTReg_address 3Dh Bit 7 Definition Access Rights Reset Value RFT 0 Bit Symbol 7-0 - 6 5 4 3 RFT RFT RFT RFT 0 0 0 0 Tab3-126 RFTReg register 2 1 0 RFT 0 RFT 0 RFT 0 2 1 0 RFT 0 RFT 1 RFT 1 2 1 0 RFT 0 RFT 0 RFT 0 Description Reserved for production tests.
3 FM17520 Register Set Bit 3.2.5.2 3.2.5.3 Symbol 5 HPDEn 4-0 RFT Description Low power mode control. Set to 0: chip enter into DPD mode combined with pin NPD=0, and register LPCDEn=0 (default value). Set to 1: chip enter into HPD mode combined with pin NPD=0, and register LPCDEn=0 (default value). (When setting with HPDEn=0, LPCDEn=1, chip enter into LPCD mode. ) Reserved for production tests. Please keep all zero.
4 Host Interfaces 4 Host Interfaces 4.1 SPI Interface A serial peripheral interface (SPI compatible) is supported by FM17520 to enable high-speed (up to 10Mbit/s) communication to the host. The FM17520 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. 4.1.
4 Host Interfaces 4.2.1 Write Extended Register The procedure for writing common registers of FM17520: 1. write address of target common register, and set writing mode meanwhile 2. write data to target common register The procedure for writing an extended register is as following 4 steps: 1. write 0F address, and set writing mode(according to SPI specification) 2. write secondary address of target extended register(01b + 6-bit secondary address) 3.
5 Analog Interface And Contactless UART 5 Analog Interface And Contactless UART 5.1 General FM17520 supports the external host online with framing and error checking of the contactless protocol requirements up to 848 kBd. It is supported thar an external circuit can be connected to the communication interface pins TIN and TOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host.
5 Analog Interface And Contactless UART Tx1RF En Bit Force10 Tx2 InvTx2 InvTx2 Enve 0ASK CW RFOn RFOff lope Bit Bit Bit Bit 1 X 0 X 1 X 1 0 1 Tab5-2 GSPMos GSNMos X RF_n pCW nCW X 0 1 0 1 X 0 RF 0 RF_n RF nMod nCW nMod nCW nCW X X RF_n pCW 0 1 Pin TX2 pMod pCW pMod pCW pCW nCW Remarks always CW forthe Tx2CW bit 100 % ASK: pinTX2 pulledto logic 0(independe nt oftheInvTx2 RFOn/InvTx 2RFOff bits) Controlling signals and settings on pin TX2 The following abbreviations have been used
6 CRC Coprocessor 6 CRC Coprocessor The following CRC coprocessor parameters can be configured: The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting The CRC polynomial for the 16-bit CRC is fixed to x16+x12+x5+1 The CRCResultReg register indicates the resultof the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes.
7 FIFO Buffer 7 FIFO Buffer FM17520 implements an 8*64 bit FIFO buffer.It buffers the input and output data streambetween the host and the FM17520’s internal state machine. This makes it possible tomanage data streams up to 64 bytes long without the need to take timing constraints intoaccount. 7.1 Accessing FIFO Buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register.
8 Interrupt Request System 8 Interrupt Request System The FM17520 indicates certain events by setting the Status1Reg register’s IRq bit and, ifactivated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 8.1 Interrupt Sources Overview Tab 8-1 shows the available interrupt bits, the corresponding source and the condition for its activation.
9 Timer 9 Timer FM17520 implements a timer unit internally. The external host controller may use the timer to manage timing relevant tasks. The timer unit may work in one of the following modes: Time-out counter Watch-dog counter Stop watch Programmable one-shot Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time.
10 Power Reduction Modes 10 Power Reduction Modes FM17520 supports three power reduction modes and can adapt to different power requirements: Deep Power Down mode Hard Power Down mode Soft Power Down mode 10.1 Deep Power Down The Deep Power Down mode of FM17520 turns off all digital circuit’s supply and the oscillator. All bi-directional I/O pins are set to three-state output, while all input pins are separated from internal circuit.
10 Power Reduction Modes Register TxASKReg RxSelReg 15h 17h RxThresholdReg 18h DemodReg 19h ModWidthReg RFCfgReg 24h 26h GsNReg 27h CWGsPReg ModGsPReg 28h 29h TModeReg 2Ah TPrescalerLoReg TreloadValHiReg TReloadValLoReg 10.
11 Low Voltage Detection 11 Low Voltage Detection FM17520 could detect supply’s voltage and alarm when its voltage is low enough. The monitoring voltage can be configured by setting the LVDctrl register. As default, interrupt and alarm will occur when AVDD voltage is once lower than the monitoring one. The LVDctrl register can also be configured as low voltage reset mode. But that mode will limit the minimum operating voltage. FM17520 Contactless Transceiver IC Ver 1.
12 Oscillator Circuitry 12 Oscillator Circuitry Fig12-1 Quartz crystal connection The FM17520’s clock provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry.
13 Reset And Oscillator Start-Up Time 13 Reset And Oscillator Start-Up Time 13.1 Reset Timing Requirements The reset signal is filtered bya spike filter before it enters thedigital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,the signal must be LOW for at least 100 ns. 13.
14 Command Set 14 Command Set 14.1 General Description The FM17520 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 14.2 General Behavior Each command that needs a data bit stream(or data byte stream) as an input immediately processes any data in the FIFO buffer.
14 Command Set 14.3.3 Generate RandomID This command generates a 10-byte random number and then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the FM17520 returns to Idle mode. 14.3.4 CalcCRC The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes.
14 Command Set In total 12 bytes are written into the FIFO. Remark: When the Authent command is active, all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set. This command automatically terminates when the M1 card is authenticated and theStatus2Reg register’s Crypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode.
15 Testsignals 15 Testsignals 15.1 Testbus The testbus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the FM17520. The testbus allows to route internal signals to the digital interface. The testbus signals are selected by accessing TestBusSel in register TestSel2Reg.
15 Testsignals 15.2 Testsignals at pin AUX1/AUX2 SelTest Description for AUX1/AUX2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Tristate DAC: register TestDAC 1/2 DAC: testsignal corr1 RFU DAC: testsignal MinLevel DAC: ADC_I DAC: ADC_Q RFU RFU RFU High Low TxActive RxActive Subcarrier detected TstBusBit Tab15-7 Testsignals description Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg.
16 Typical Application Diagram 16 Typical Application Diagram The figure below shows a typical application diagram based on FM17520. PVDD2 PVDD DVDD AVDD TVDD C3 RX R2 NPD CONTROLLER IRQ C4 FM17520 TX1 R1 VMID C1 L0 C0 Rq C2 TVSS Lant C2 C0 DVSS C1 PVSS TX2 AVSS Rq L0 OSCOUT OSCIN 27.12MHz Fig16-1 Typical application diagram FM17520 Contactless Transceiver IC Ver 1.
17 Characteristics 17 Characteristics 17.1 Limiting Values Parameter Min Max Unit Storage temperature -40 +85 °C AVDD, DVDD, TVDD,PVDD,PVDD2 -0.5 4.0 V 2 KV ESD（HMB） 500 V ESD（CDM） Tab17-1 FM17520 limiting values *Remark: Any conditions beyond the limiting values will bring permanent damage to the device. 17.
17 Characteristics Symbol tWH th（SCKH-D） Parameter Conditions pulse width HIGH line SCK SCK HIGH to data input hold time SCK to changing MOSI changing MOSI to SCK SCK to changing MISO Min 50 Typ Max Unit 25 ns 25 data input to SCK HIGH tSU（D-SCKH） set-up time 25 SCK LOW to data output hold th（SCKL-Q） time t（SCKL-NSSH） SCK LOW to NSS HIGH time 0 NSS high before tNHNL 50 communication Tab17-3 SPI AC characteristics ns ns 25 ns ns ns Fig17-1 Timing diagram for SPI Remark: The signal NSS must b
18 Ordering Information 18 Ordering Information Device Number Package Wrap FM17520-QNA-A-G QFN32 Tray FM17520 Contactless Transceiver IC Ver 1.
19 Package Information 19 Package Information 19.1 QFN32 Package Outline Fig19-1 FM17520 QFN32 Package Outline FM17520 Contactless Transceiver IC Ver 1.
Revision History Revision History Rev 1.0 Release Date Oct.2016 Pages FM17520 Contactless Transceiver IC 69 Chapters/Ta bles/Figures Modifications Initial Release. Ver 1.
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FCC Statement This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. The device has been evaluated to meet general RF exposure requirement.
