Schematics

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RF
Power & GND
Interface & GPIO
(LED_WL)
(COEX2)
(COEX1)
(COEX3)
(SD_RST)
VDD33
ANTSW
ANTSWB
RFIO_BT
RFIO_W L2G_S0
RFIO_W L2G_S1
RFIO_W L5G_S0
RFIO_W L5G_S1
RFIP_WL5G_S1
RFIP_WL5G_S0
S1_PAPE_5G
S1_TRSWB
S0_PAPE_5G
S0_TRSWB
RFIO_W L5G_S0
RFIP_WL5G_S0
RFIO_W L2G_S0
ANTSW
RFIO_W L2G_S1
RFIO_W L5G_S1
RFIO_BT
RFIP_WL5G_S1
ANTSW
S0_TRSWB
S0_PAPE_5G
VDD33
VD10
VD10
VD10
VDD33
VDD33
VD10
VDD33
VDD_IO
VDD33
VDD_IO
VDD33
VD33_SPS
VD10
VDD33
VD10
VD10
VD10
VDD33
LX_SPS
VDD33
VDD33
VDD33
VD10
VD10
RF_S0
UART_TX
BT_LOG
SUSCLK
SD_D1
SD_WAKE
SD_CLK
UART_RX
#TEST_MODE_SEL
SD_CMD
BT_WAKE
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
UART_CTS
COEX3
UART_WAKE
SD_D2
VDD_IO
SD_D3
SD_D0
WL_DIS_N
BT_DIS_N
WL_DIS_N
SD_WAKE
SD_CMD
SD_CLK
SD_D3
SD_D2
SD_D0
SD_D1
PCM_IN
PCM_OUT
PCM_CLK
SUSCLK
VDD_IO
VDD33
UART_WAKE
BT_WAKE
UART_CTS
UART_RX
UART_TX
BT_DIS_N
PCM_SYNC
ANTSWB
S1_PAPE_5G
S1_TRSWB
#SPS_LDO_SEL
RF_S0
RF_S1
SD_RESET
SD_RESET
#TEST_MODE_SEL
VD10
VDD_IO
RF_S1
VDD_IO
C44 0u1F
C50 0u1F
C114
1uF
C38 0u1F
C97 22pF
C98 1p5F
C22
10pF
SW2
SPDT
O2
3
V2
4
O1
1
V1
6
G
2
IN
5
G
7
LGA1
LGA_1315
GND
1
WL/BT_ANT0
2
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
WL_ANT1
9
GND
10
GND
11
NC
12
NC
13
NC
14
WL_REG_ON
15
WL_WAKE_HOST
16
SDIO_CMD
17
SDIO_CLK
18
SDIO_DATA3
19
SDIO_DATA2
20
SDIO_DATA0
21
SDIO_DATA1
22
GND
23
OOB
24
NC
25
NC
26
PCM_SYNC
27
PCM_IN
28
PCM_OUT
29
PCM_CLK
30
LPO
31
GND
32
NC
33
VDDIO
34
NC
35
VBAT
36
NC
37
BT_REG_ON
38
GND
39
UART_TXD
40
UART_RXD
41
UART_RTS_N
42
UART_CTS_N
43
SD_RESET
44
NC
45
NC
46
NC
47
NC
48
HOST_WAKE_BT
49
BT_WAKE_HOST
50
100kR
R10
C54 1uF
23 balls
U1A
TFBGA_7
RFIO_BT
A2
RFIO_W L5G_S1
D1
RFIP_WL5G_S1
C1
RFIO_W L5G_S0
J1
RFIP_WL5G_S0
H1
RFIP_WL2G_S0
L2
RFIO_W L2G_S0
L1
S1_PAPE_5G
D6
S1_PAPE_2G
E5
S1_TRSW
F6
S1_TRSWB
F5
S1_TSSI
D5
S0_PAPE_5G
G6
S0_PAPE_2G
H5
S0_TRSW
K7
S0_TRSWB
H6
ANTSW
D4
ANTSWB
E4
XI
L5
XO
L6
RFIP_WL2G_S1
G1
RFIO_W L2G_S1
F1
S0_TSSI
G5
C65
0u1F
C88 1uF
C5
10pF
LV7 3n3H
C55 0u1F
C84 22pF
C43 0u1F
C53 0u1F
C20
1p5F
C110
10pF
C103
NP
C42 0u1F
C90
10pF
C39 0u1F
31 balls
U1B
TFBGA_7
VD33_AFE_BT
C5
VD1_AFE_BT
A5
VD1_BT
A1
VD1_SYN_BT
A4
VD10D_BT
A6
VDDIO_HOST / VD33_USB
A8
VD33_SYN_BT
C4
VD33_PA_WLS1
E1
VD33_PAD_W LS1
E2
VD1_USB
B8
VD33_PA_WLS0
K1
VD33_IO
L10
VD1_RF_WLS0
G2
VD1_AFE_WL
L7
VD33_PAD_W LS0
J2
VD33_SYN_WL
L4
VD33X
K6
VD33_SPS
L11
LX_SPS
K11
LX_SPS
K10
VD10D_FB_WL
L9
VD1_VDDTX
C10
VD1_VDDRX
B9
VD33_PA_BT
A3
VD1_SYN_WL
L3
VD1_RF_WLS1
B1
VDDIO_2
L8
CAP_XTAL
J5
VD10D_WL
H11
VDDIO_1
B7
VD33_IO
A7
C119 0u1F
SW1
SPDT
O2
3
V2
4
O1
1
V1
6
G
2
IN
5
G
7
XTAL1
40MHz
XTALP
1
2
2
XTALP
3
4
4
C101 22pF
C66 10uF
C76
10uF
C45 0u1F
20 balls
U1C
TFBGA_7
HSDP / UART_CTS
A11
HSDM / UART_RX
A10
HSIP / SDIO_CLK
B11
HSIN / SDIO_CMD
C11
REFCLK_P / SDIO_D2
F11
REFCLK_N / SDIO_D3
G11
HSOP / SDIO_D0
D11
HSON / SDIO_D1
E11
PERSTn / GPIO10
E10
CLKREQn / GPIO15
F10
WAKEn / CHIP_EN
F9
BT_LED[1]
E8
RREF / UART_RTS
A9
BT_LOG
E6
EECS
C9
EESK
J10
NFC_RF_DIS
F7
NFC_INT
F8
NFC_CLK
G7
NFC_DATA
G8
220R
R6
47kR
R22
C51 0u1F
LV3 1n2H
C29
15pF
C69 0u1F
C74
10uF
C64 1uF
C92
10pF
C36 2p7F
47kR
R23
LV1 1n2H
SW3
SP3T
V1
3
RF1
4
RFC
1
V2
6
NC
2
RF2
5
GND
9
V3
7
RF3
8
DX1
DPX
RF1
2
GND
1
WL_2G1
3
WL_5G1
4
47kR
R20
C30
15pF
C109 10pF
C10
1p2F
47kRR21
LV2 2n2H
C68 1uF
C63 0u1F
LV6 2n4H
C102
10pF
C21
1p8F
C9
1p5F
C49 0u1F
14 balls
U1D
TFBGA_7
GPIO[4]
H7
GPIO[5]
J9
GPIO[0]
J8
GPIO[1]
H8
GPIO[2]
H9
GPIO[3]
H10
GPIO[13]
D10
GPIO[6]
D7
GPIO[7]
D8
GPIO[12]
D9
GPIO[9]
C8
GPIO[11]
C7
GPIO[8]
E7
GPIO[14]
E9
C111 10pF
LV5 3n0H
C115 1uF
C23 0u1F
C99 10pF
LV8 2u2H
C113
10pF
33 balls
U1E
TFBGA_7
UART_TX / GND_HCI
B10
GND_SPS
J11
GND_RF1_WL
C2
GND_RF1_WL
C3
GND_RF2_WL
D2
GND_RF2_WL
E3
GND_RF2_WL
F4
GND_RF3_WL
G3
GND_RF2_WL
G4
GND_RF4_WL
H3
GND_RF4_WL
H2
GND_CORE
G10
GND_BALUN_BT
B3
GND_CORE
C6
GND_CORE
B6
GND_SYN_WL
K4
GND_AFE_WL
J6
GND_AFE_BT
B5
GND_SYN_BT
B4
GND_RF_BT
B2
GND_RF2_WL
D3
GND_RF2_WL
F2
GND_RF2_WL
F3
GND_RF4_WL
H4
GND_RF4_WL
J3
GND_RF4_WL
K2
GND_RF4_WL
K3
GND_CORE
G9
GND_CORE
K8
GND_CORE
K9
GND_AFE_WL
J7
GND_XTAL
K5
GND_RF4_WL
J4
C62 1uF
47KR R18
C52 0u1F
C3
0p5F
R13 6.8R
C94 10pF