Hardware Guide

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G2
GNSS_ANT_L1
-
-
-
GNSS L1 ANT
Leave this pin
open(floating)
GNSS_ANT_L1
E2
GNSS_ANT_L5
-
-
-
GNSS L5 ANT
Leave this pin
open(floating)
GNSS_ANT_L5
Antenna switching
M8
RFFE_DATA
1.8
O
-
MIPI DATA for ANT
switch at TCU side
Ant switch
Ant switch
N9
RFFE_CLK
1.8
O
-
MIPI CLK for ANT
switch at TCU side
Ant switch
Ant switch
E12
GPADC2
1.8
I
-
Connect to GND if
unused
Ant switch (ADC)
Ant switch (ADC)
PCIE Interface
L33
PCIE1_REFCLK_N
0.85
B
-
PCIE REF CLKN
AP_PCIe0_REFCLK_N
AP_PCIe0_REFCLK_N
L35
PCIE1_REFCLK_P
0.85
B
-
PCIE REF CLKP
AP_PCIe0_REFCLK_P
AP_PCIe0_REFCLK_P
J33
PCIE1_RXD_N
0.85
O
-
PCIE TXDN at CP
side
AP_PCIe0_RX_N
AP_PCIe0_RX_N
J35
PCIE1_RXD_P
0.85
O
-
PCIE TXDP at CP
side
AP_PCIe0_RX_P
AP_PCIe0_RX_P
K34
PCIE1_TXD_N
0.85
I
-
PCIE RXDN at CP
side
AP_PCIe0_TX_N
AP_PCIe0_TX_N
K36
PCIE1_TXD_P
0.85
I
-
PCIE RXDP at CP
side
AP_PCIe0_TX_P
AP_PCIe0_TX_P
N29
PCIE1_CLK_REQ_N
1.8
B
PU
PCIE Clock
Request_N
NAD_PCIe_CLK_REQn
NAD_PCIe_CLK_REQn
H9
PCIE1_RST_N_RC
1.8
O
PCIE Reset as NAD
Leave this pin
open(floating)
NAD_PCIe_RSTn
O36
PCIE2_REFCLK0_N
0.85
B
-
PCIE REF CLKN
Leave this pin
open(floating)
PCIE2_REFCLK0_N
O34
PCIE2_REFCLK0_P
0.85
B
-
PCIE REF CLKP
Leave this pin
open(floating)
PCIE2_REFCLK0_P
M34
PCIE2_RX0_N
0.85
O
-
PCIE TXDN at CP
side
Leave this pin
open(floating)
PCIE2_RX0_N
M36
PCIE2_RX0_P
0.85
O
-
PCIE TXDP at CP
side
Leave this pin
open(floating)
PCIE2_RX0_P
N33
PCIE2_TX0_N
0.85
I
-
PCIE RXDN at CP
side
Leave this pin
open(floating)
PCIE2_TX0_N
N35
PCIE2_TX0_P
0.85
I
-
PCIE RXDP at CP
side
Leave this pin
open(floating)
PCIE2_TX0_P
N31
PCIE2_CLK_REQ_N
1.8
B
PU
PCIE Clock
Request_N
Leave this pin
open(floating)
PCIE2_CLK_REQ_N
M30
PCIE2_RST_N
1.8
O
-
PCIE Reset as NAD
Leave this pin
open(floating)
PCIE2_RST_N
SPI Interface
Q12
CP_SPI_CLK
1.8
I/O
-
SPI Clock
NAD_SPI_CLK
NAD_SPI_CLK
Q10
CP_SPI_CSN
1.8
I/O
-
SPI Chip Select
NAD_SPI_CSn
NAD_SPI_CSn
R11
CP_SPI_MISO
1.8
O
-
SPI TX DATA
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
mode)
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
mode)
R9
CP_SPI_MOSI
1.8
I
-
SPI RX DATA
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
mode)
NAD2_SPI_MISO(slave
mode)
NAD_SPI_MOSI(master
mode)
AP / MCU ↔ CP Interface
Q26
CP_PMIC_PWR_EN
1.8
I
-
CP Power on input
NAD_PMIC_EN
NAD_PMIC_EN
C28
CP_RESETB
1.8
I
-
External Reset
Input
NAD_RSTn
NAD_RSTn
F31
CP_CLK_32K
1.8
I
-
CP sleep clock /
input
NAD_RTC
NAD_RTC
I2S Interface
C6
SPEECH_I2S_BCK_CP
1.8
I
-
Audio I/F Clock
NAD_I2S_BCK
NAD_I2S_BCK
C8
SPEECH_I2S_D_IN_CP
1.8
I
-
Audio I/F Serial
Data Input
NAD_I2S_DIN
NAD_I2S_DIN