Hardware Guide

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Hardware Guide
3.5 PCIe Interface
The module provides PCIe interface.
- PCIe base specification, Revision 4.0 specification, version 1.0
- Maximum of 16 Gbps (Gen4) for PCIe dual mode (pin-selectable EP/RC)
- Two lanes for Tx and Rx up to Gen4
- 32-bit pipe width per lane
- AXI3 bridge
- Internal Address Transmission Unit (ATU) (three outbound regions, five inbound regions, 4000 minimum region
size)
- 256 bytes (maximum) payload size
- 32 (maximum) outbound NP requests
- One virtual channel
- L1 sub-states
- Dedicated Data Bus Interface (DBI) slave
- PCIe Interrupt Aggregator (IA) with sequencer
It is recommended that the differential clock output signals of PCIe interface should be connected as Figure 3-5. Two
220nF capacitors inner module are separately placed on the TX signal in series. In addition, two 220nF capacitors
placed on the differential clock output signals in series are used for DC blocking.
Figure 3-5 Recommended circuit of the PCIe interface(CP only)