User Manual Part 1

CIRCUIT ANALYSIS
30 MM101271V1 R2A
7.3.2.9 Decouplers
Decoupling capacitors (Decouplers) are used to eliminate high-speed transient noise in
high-speed digital circuits. There are many decoupling capacitors used on the Controller
Board. These capacitors are connected between a source and ground. For example, on
sheet 3 of Schematic Diagram WD-CB101069V1 there are two 3.3V decoupling
capacitors, C2 and C87.
7.3.3 Backplane
The Controller Board to Interconnect Board A1 (Backplane) connector circuits are shown
on Schematic Diagram WD-CB101069V1, Sheets 4-7 and include:
• Board Connections • I/O (1)
• Serial I/O • I/O (2)
7.3.3.1 Board Connections
Schematic Diagram WD-CB101069V1, Sheet 4 shows the single DIN96 connector, J7.
This 96-pin connector has three layers of pins, J7A, J7B and J7C. Each layer consists of
32 pins. J7B, Pins 1 and 32 are the MATE-DETECT-A and MATE DETECT-B
connections. These two connections are used with the Board Insertion Detection circuit.
Pins J7B; Pins 27 and 28 are the SCL and SDA connections. SCL and SDA make up the
I
2
C bus. CPU I/O SIGNAL PROTECTION DIODES D27, D29 connected to SCL and
SDA provide surge protection for the I
2
C bus.
7.3.3.2 Serial I/O
Numerous asynchronous and synchronous serial ports are brought to the Interconnect
Board (Backplane) from the microprocessor, Modem Board and QUART. Most serial
ports convert to standard RS-232 levels using RS-232 transceivers U13, U24, U30 &
U36. Serial port U21 converts to RS-485 differential signal levels and supports a
multidrop network. One microprocessor RS-232 port is used as a diagnostic or local
programming port and is brought to RJ-11 connector J8 on the front of the board. Two
ports from the QUART use BSL signaling.
All Serial ports are designed for full-duplex 115.2 kbaud communications with the
exception of the RS-485 port U21 from the microprocessor SCC. This port is a half-
duplex HDLC port and supports speeds up to 2 Mbaud.
U21 is a differential bus transceiver for bi-directional data communication on multiport
bus transmission lines. This device combines a 3-state differential line driver and a
differential input line receiver. The driver and receiver have active-high and active-low
enables that are connected together externally to function as a direction control. The
driver differential outputs and the receiver differential inputs are connected internally to
form differential input/output I/O bus ports. These ports are designed to offer minimum
loading to the bus when the driver is disabled or Vcc=0.
BSL signaling is accomplished through two identical circuits consisting of hex inverting
Schmitt Triggers U23A/U23B, inverter buffer drivers U35A/U35B, Field Effect
Transistors (FET) Q3/Q4, NPN transistors Q9/Q10 and diodes D23/D25. Inputs to the
microprocessor from the Interconnect Board (backplane) are through diode D23/D25 to
the input of U23A/U23B. Schmitt Trigger U23A/U23B provides a well-defined output