User Manual Part 1

CIRCUIT ANALYSIS

MM101271V1 R2A 35

Table 5 - External Chip Select Signals

DEVICE IRQ MACHINE DATA BUS WIDTH

FLASH CS0 GPCM 32 Bit

SDRAM CS1 UPMA 32 Bit

QUART REGISTERS CS2 GPCM 8 Bit

QUART INTERRUPT VECTOR CS3 GPCM 8 Bits

EPLD CS4 GPCM 8 Bits

MODEM DUAL PORT RAM CS5 UPMB

8 Bits

MODEM CODE RAM CS6 GPCM 8 Bits

(SPARE-EPLD) CS7 N/A N/A

Note that there is both a 32-bit data bus and an 8-bit data bus. The 8-bit data bus is

connected to the 32-bit processor data bus via an 8-bit transceiver. The output enable for

the transceiver is controlled by ANDing all 8-bit chip selects together inside the EPLD.

7.3.4.2 Microprocessor Support

The microprocessor support as shown on Schematic Diagram WP-CB101069V1, Sheet 9

includes:

• BDM Debug Port Connector • Silicon Serial Number

• Power-On Reset Configuration • KAPWR Switch

• 32 kHz Crystal • 8-Bit Bus Transceiver

• VDDSYN Filter • MICTOR Logic Analyzer Connectors

BDM Debug Port Connector

For debug and development, microprocessor U9A provides a dedicated serial port (BDM)

for connecting a debugger/emulator. A debugger/emulator connected to this port allows a

programmer to read/write registers and external peripherals, control program execution,

etc. Many debuggers also have built-in capability to program on-board flash through this

port. These serial port pins are brought to 10-pin header J1 using the standard BDM

pinout.

Power-ON Reset Configuration

The Power-On Reset Configuration consists of four octal buffer/drivers U6A, U6B, U8A

and U8B with 3-state outputs. This circuit ensures that at Power-On all circuits are reset

to the starting state. Inputs to these circuits are through 10K BUS8 resistor networks RN7

and RN10. The outputs tie into bus D[0.31]. Each package is organized as two 4-bit line

drivers with separate output-enable (OE) inputs. These inputs are tied together and

connect to RESET-N. When RESET-N is low, data passes from A inputs to Y outputs.

When RESET-N is high, the outputs are in the high-impedance state. This circuit imposes

UPMB is only required if the system makes use of the BUSY_N signal coming from the dual port memory. If BUSY_N is

not used, then a GPCM machine can be used for this chip select.