User Manual Part 1

CIRCUIT ANALYSIS
36 MM101271V1 R2A
predetermined "start-up" information on the microprocessor data bus during RESET. The
microprocessor reads the data bus state just before RESET goes inactive (high) and uses
the result for start-up initialization.
At power up, the MPC860 samples the data bus and the MODCK bits to obtain the
Hardware Configuration Word and clock setup parameters respectively. The SitePro
hardware configures these as follows:
Data bus 0x017A 0000
MODCK1, 2 1,0
This results in the following configuration:
Internal arbitration
Interrupt vector location 0xFFF0 0000
Boot Port size is 32 bits.
IMMR is at 0xFF00_0000.
Debug Pin Configuration is as follows: VFLS[01], VF0, VF1, STS, AT1, AT2, AT0,
AT3, OP3.
Debug Port Pin Configuration is DSCK, DSD1, DSD0, PTR1, TCK, TD1 and TD0.
External Bus speed set to ½ system clock.
Pitrtc connected to extclk and div by 4, pitclk = 32.768/4 = 8192 Hz
Sys clk connected to EXTCLK vco factor is 1, sysclk = 29.4912 MHz
32 kHz Crystal
This crystal circuit consists of crystal package Y3, resistors R90 and R98, capacitors C49
and C63. This circuits connects to microprocessor U9A between pins N1 (EXTAL) and
P1 (XTAL) and produces an oscillator frequency of 32.768kHz to drive the real-time
clock.
29 MHz Clock
The 29 MHz Clock consists of oscillator circuit Y2 and resistors R82 and R105. This
circuit produces the oscillator frequency of 29.4912 MHz and connects to microprocessor
U9A at N2 (EXTCLK).
VDDSYN Filter
This circuit consists of inductor L1 and capacitors C50 and C57. It filters the 3.3V supply
to the system Phase-Locked-Loop (PLL) circuitry on microprocessor U9A. The PLL
multiplies the EXTCLK by an integer factor to provide a bus clock.
Silicon Serial Number
A unique 64-bit electronic Serial Number chip U3 is used to store the board identification
number. This chip has a 1-bit serial port, which interfaces to microprocessor U9 through
an I/O port. In addition, four bits of hardware identification are made available to U9
through I/O ports. The Hardware ID is changed by selectively populating a bank of
resistors.