User Manual Part 1

CIRCUIT ANALYSIS
40 MM101271V1 R2A
Table 8 - DRAM Bank Memory Ranges
BANK 64-MBIT (DRAM) 128-MBIT (2XDRAM) 256-MBIT (SDRAM)
Bank 1 0x003FFFFF – 0x00000000 0x003FFFFF – 0x00000000
0x013FFFFF – 0x01000000
0x003FFFFF – 0x00000000
0x013FFFFF – 0x01000000
0x023FFFFF – 0x02000000
0x033FFFFF – 0x03000000
Bank 2 0x007FFFFF – 0x00400000 0x007FFFFF – 0x00400000
0x017FFFFF – 0x01400000
0x007FFFFF – 0x00400000
0x017FFFFF – 0x01400000
0x027FFFFF – 0x02400000
0x037FFFFF – 0x03400000
Bank 3 0x00BFFFFF – 0x00800000 0x00BFFFFF – 0x00800000
0x01BFFFFF – 0x01800000
0x00BFFFFF – 0x00800000
0x01BFFFFF – 0x01800000
0x02BFFFFF – 0x02800000
0x03BFFFFF – 0x03800000
Bank 4 0x00FFFFFF – 0x00C00000 0x00FFFFFF – 0x00C00000
0x01FFFFFF – 0x01C00000
0x00FFFFFF – 0x00C00000
0x01FFFFFF – 0x01C00000
0x02FFFFFF – 0x02C00000
0x03FFFFFF – 0x03C00000
7.3.9.2 FLASH
Two flash memory chips U10 and U11 are organized as 1M x 32 for non-volatile
program storage (Flash). These two chips have 4 Mbytes of flash memory with the
ability of expansion up to 8 Mbytes. One or more flash sectors contain "bootloader" code,
which contains enough functionality to load and store new versions of application code.
7.3.9.3 Quad UART
The QUART circuit for the Controller Board is shown on Schematic Diagram WD-
CB101069V1, Sheet 17.
Quad Universal Asynchronous Receiver-Transmitter (QUART) U28 is used to handle
asynchronous serial data communication.
The serial port is a general-purpose interface that conforms to the Recommended
Standard–232C (RS-232C) and can be used to interface with almost any type of device
(modem, mouse and serial printer, etc.).
Quad UART U28 provides four additional serial ports for microprocessor U9. U28 is
powered by 3.3V, which forces the microprocessor interface to be asynchronous and run
at 14.75 MHz, the microprocessor bus clock divided by 2 inside the EPLD. The
communication clock input is 3.6864 MHz, the microprocessor bus clock divided by 8
inside the EPDL. None of the I/O ports of the QUART are used at this time.
The QUART uses two chip selects, CS2 and CS3. Chip select CS2 is used when
accessing the QUART registers. Chip select CS3 is used after an interrupt to read the
interrupt vector.