User Manual Part 1

TROUBLESHOOTING
MM101271V1 R2A 67
(RFTXD). It exits on U27-38 (RFTXDAT), is buffered and inverted by U29F, entering
on U29-13, exiting on U29-12. It exits the Board on J7-C23.
At the rear of the shelf, RFTXDAT is looped back into the Controller board on J7-C26
(RFRXDAT_FROM_SLICER). This signal is buffered and inverted by U29D, entering
on U29-9, exiting on U29-8, which drives into the PLD U27-53. It exits the PLD on U27-
99 (RFRXD). This goes to the Modem Board on J2-7. On the Modem Board, it goes to
U9-19 completing the loop.
Refer to RF Loop Test Block Diagram in the instruction book.
This test may fail due to problems in the microprocessor U1 interface to the Modem IC
U9. This includes 3V/5V converter U6, U21, U23, U16C and perhaps address decoder
U5 or U16A. Many negative going interrupt pulses should be seen on U9-24. Check R11.
9.4.3.5 MODEM BER TEST ON PL MODEM
Procedure:
This is the same as the shelf PL loopback test. Reset the Modem Board. SIMON
Commands are MDS1 then BERDE-01=1. Correct result is no errors and
checksum=027C11.
Troubleshooting information:
After running the BER test on the RF Modem (above), SIMON code requires a reset
before running the BER test on the Phone Line Modem. This can be accomplished by
using FactoryTest to execute test 4, subtest 3 (Dual Port RAM test). This will reset the
Processor then unreset it without affecting loaded code.
SIMON causes a data stream to be generated in PL Modem U10 at U10-21 (PLTXDAT).
This data goes to the Controller Board on J2-9 where it enters the PLD at U27-31
(PLTXD). It exits on U27-23 (PLTXDAT), is buffered, inverted and converted to RS232
levels by U30, entering on U30-7, exiting on U30-2. It exits the Board on J7-B19.
Data is passed through the Rockwell Modem then, at the rear of the shelf, PLTXDAT is
looped back through the Rockwell Modem and into the Controller board on J7-B21
(PLRXDAT). This signal is buffered, inverted and converted back to TTL levels by U30,
entering on U30-9, exiting on U30-8, which drives into the PLD U27-25. It exits the PLD
on U27-34 (PLRXD). This goes to the Modem Board on J2-29. On the Modem Board, it
goes to U10-19 completing the loop.
Refer to PL Loop Test Block Diagram in the instruction book.
This test may fail due to problems in the microprocessor U1 interface to the Modem IC
U10. This includes 3V/5V converter U6, U21, U23, U16C and perhaps address decoder
U5 or U16A. Many negative going interrupt pulses should be seen on U10-24. Check
R12
9.4.3.6 TEST LSDIN
Procedure:
Apply 100Hz 1VPP sine wave to J12-7. This should produce a 0 to 5V 100Hz square
wave at Controller Board connector J7-C10. Observe 3VPP 100Hz square wave at U1-2
on the Modem Board.