User Manual Part 1

TROUBLESHOOTING
MM101271V1 R2A 77
Jumper VDIRTS to VDICTS, J14B-6 to J14B-7 on the shelf rear.
Then execute FactoryTest test 16.
Troubleshooting information:
Upon command of the 860 processor, PLRTS is generated in the PLD and exits U27-65.
It is buffered, inverted and converted to RS232 levels by U13, entering U13-11, exiting
U13-14. It exits the board on J7-B18.
PLRTS is looped back to the Controller board into PLCTS on J7-B17. It is converted to
TTL, buffered and inverted by U13, entering U13-13 and exiting U13-12. It enters the
PLD on U27-83 where it can be read by the 860 processor.
Upon command of the 860 processor, VDIRTS is generated in the PLD and exits U27-63.
It is buffered, inverted and converted to RS232 levels by U13, entering U13-10, exiting
U13-7. It exits the board on J7-C18.
VDIRTS is looped back to the Controller board into VDICTS on J7-C17. It is converted
to TTL, buffered and inverted by U13, entering U13-8 and exiting U13-9. It enters the
PLD on U27-82 where it can be read by the 860 processor.
9.4.3.27 PHASE LOCKED LOOP TEST AND TXC_MISSING_ALARM TEST
Procedure:
Use a Function Generator to produce a 0V to 5V 9600Hz square wave. Apply this across
J13-13 & 14 (9.6REF+ and -), with the ground side connected to J13-14.
Execute FactoryTest test 14, subtest 1. Ignore the first line of the on screen instructions
since the input is applied differently. Use a dual trace scope as described to check for two
signals in phase. RFTXCLK is also seen at J11-14.
Troubleshooting information:
This test uses PLL IC U16 to phase lock the RFTXCLK used by the RF Modem U9 on
the SitePro Modem Board to an external reference signal 9.6REFIN. The PLL chip
generates an 11.0592 MHz clock slaved to the external reference. In the PLD, this clock
is switched to the Modem board instead of the 11.0592 MHz. oscillator clock. Modem
Board IC U9 divides the 11.0592 MHz back down to 9.6kHz (RFTXCLK) which is
phased locked by the PLL U16. Both the reference and the feedback signals are switched
to the PLL inside the PLD.
A Modem board must be present for this test and it must not be held reset. The Modem
board is normally held reset by the Controller until it is explicitly unreset. It can be
unreset by loading code such as SIMON to it. It can also be unreset by executing Factory
Test 4, subtest 3, (Test Dual Port RAM).
9.6REFIN enters the Controller board at TTL levels on J7-C15. It is buffered and
inverted by U22F, entering in U22-13, exiting on U22-12. It enters the PLD on U27-69.
RFTXCLK is derived from the 11.0592 MHz clock on the Modem Board by U9, exiting
on U9-27. It is routed to the Controller board through J2-8 (Modem board) which
connects to Controller Board J2-8. It enters the PLD on U27-128.
If the loop fails to lock, one or both signals 9.6REFIN or RFTXCLK may not be getting
to the PLL U16. U16 or some of the associated components may be wrong, misoriented