User Manual Part 1

TROUBLESHOOTING
78 MM101271V1 R2A
or missing. Use a known good Modem board. Check for 11.0592 MHz clock at Modem
Board U9-16.
Procedure:
Instead of following the on screen directions, observe TXC_MISSING_ALARM at J13-
18. The test requires an external pullup resistor.
Remove the 9.6REF signal. TXC_MISSING_ALARM should go high.
Troubleshooting information:
TXC_MISSING_ALARM is generated inside the PLD if 9.6REFIN is missing.
9.6REFIN must get to the PLD via the path described above. The
TXC_MISSING_ALARM signal exits the PLD on U27-62. It is buffered and inverted by
U35D, entering on U35-9, exiting U35-8.
9.4.3.28 TEST PLTXCLK
Procedure:
Observe PLTXCLK (9600Hz, RS232) at J14A-4 on the rear of the shelf.
Troubleshooting information:
PLTXCLK is generated on the Modem Board at U10-27, and is inverted by U24 before
exiting the Modem Board on J2-28. It enters the PLD on U27-32. It is also buffered,
inverted, and converted to RS232 levels by U30, entering at U30-6, exiting U30-3. It
exits the Controller Board on J7-B20.
A working Modem board must be present and not reset for this test.
9.4.3.29 TEST VDITXCLK
Procedure:
Observe VDITXCLK (9600Hz, RS232) at J14B-4 on the rear of the shelf.
Troubleshooting information:
This test checks the path of VDITXCLK. It is generated on the Modem Board at U11-27,
and is inverted by U25 before exiting the Modem Board on J2-11. It is buffered, inverted,
and converted to RS232 levels by U30, entering at U30-21, exiting U30-28. It exits the
Controller Board on J7-C20.
A working Modem board must be present and not reset for this test.
9.4.3.30 FSL OUTPUT TEST
Procedure:
Execute FactoryTest test 15
Observe the FSL output at J4C-4 on the rear of the shelf.
Troubleshooting information:
The FSL signal is a series of negative going 12V to 0V pulses occurring every 30ms and
2.5ms wide.
The FSL output signal is generated in the PLD using RFTXCLK (tested above) from the