User's Manual
Table Of Contents
- 1 System Overview
- 2 Features Summary
- 3 EXACT-V2 Rack
- 3.1 EXACT-V2 mechanics
- 3.2 Interface characteristics
- 3.3 Front Panel signalization (LEDs description)
- 3.4 Power requirements
- 3.5 Performances and technical characteristics
- 3.5.1 General characteristics
- 3.5.2 Control and data Ethernet interfaces
- 3.5.3 Serial control interfaces
- 3.5.4 ASI inputs / output and MPEG-TS processing
- 3.5.5 Digital modulation
- 3.5.6 Clock synchronization
- 3.5.7 RF and monitoring outputs
- 3.5.8 Digital precorrection
- 3.5.9 Power level measurement inputs and AGC
- 3.5.10 Dry contacts
- 3.6 Conformity with EC Directive
- 4 EXACT-V2 Installation
- 5 Operation
- 6 Maintenance & Troubleshooting
- Appendix A GPS Installation Recommendations
- Appendix B Example of GPS Antenna
USER
MANUAL
MPD-1611291-A
EXACT-V2 High End Rack Modulator / Exciter
3/10/2017
MPD-1611291-A
Page 36/94
The PLL_Unlocked status (Mute on SFN Not Ready) is used in order to maintain that
the output signal is muted (please refer to the mute conditions in chapter RF output
muting and RF maintain features.)
In case of SFN application, an optional functionality “PPS auto resync” is available to
allow resynchronization of the internal PPS (used as a reference time in SFN) when
10MHz clock control is locked. This optional functionality allows having the best
accuracy on time reference PPS used for SFN systems.
The external references have to follow the recommendations specified in the interface
description § Interfaces characteristics. The switching is seamless from external
reference signal to the 10 MHz internal clock.
Note: In case both Mute conditions “Mute on LORS” and “Mute on Clock Not Synchro”
(or “Mute on SFN Not Ready”) are enabled, the Mute will occur only after the LORS
TimeOut has ended, as shown in the chronograms below:
1. Mute behaviour when:
Mute on LORS is enabled
Mute on Clock Not Synchro is enabled
LORS TimeOut is reached
Figure 17: Mute behaviour – LORS TimeOut is reached