Data Sheet

8
sensing.honeywell.com

2

SD
A
SCL
t
LOW
t
HDSTA
t
HDSTA
t
HIGH
t
HDDAT
t
SUSTA
t
SUSTO
t
BUS
t
SUDAT
     
SCLclockfrequency F
SCL
100 – 400 kHz
StartconditionholdtimerelativetoSCLedge t
HDSTA
0.1 – – µs
MinimumSCLclocklowwidth
1
t
LOW
0.6 – – µs
MinimumSCLclockhighwidth
1
t
HIGH
0.6 – – µs
StartconditionsetuptimerelativetoSCLedge t
SUSTA
0.1 – – µs
DataholdtimeonSDArelativetoSCLedge t
HDDAT
0 – 0.5 µs
DatasetuptimeonSDArelativetoSCLedge t
SUDAT
0.1 – – µs
StopconditionsetuptimeonSCL t
SUSTO
0.1 – – µs
Busfreetimebetweenstopandstartcondition t
BUS
1 – – µs

1
CombinedlowandhighwidthsmustequalorexceedminimumSCLperiod.

t
BUS
t
CLKD
SCLK
MISO
SS
t
HIGH
t
SUSS
HiZHiZ
t
HDSS
t
LOW
t
CLKD
     
SCLKclockfrequency f
SCL
50 – 800 kHz
SS drop to first clock edge t
HDSS
2.5 – – μs
MinimumSCLKclocklowwidth
1
t
LOW
0.6 – – μs
MinimumSCLKclockhighwidth
1
t
HIGH
0.6 – – μs
Clock edge to data transition t
CLKD
0 – 0.5 μs
Rise of SS relative to last clock edge t
SUSS
0.1 – – μs
BusfreetimebetweenriseandfallofSS t
BUS
2 – – µs

1
CombinedlowandhighwidthsmustequalorexceedminimumSCLKperiod.
HIH7000 Series • 