Data Sheet

LINEAR MAGNETIC FIELD SENSORS
11
Low Power— For low power application, down to 3.3 volt
supply, the circuit shown in Figure 15 can be used. These
low threshold FETs provide low on-resistance (0.3Ω) at
V
GS=2.7V. The set/reset pulsing does not need to be
continuous. To save power, the SET pulse can be initially
applied followed by a single RESET pulse. The offset (OS)
can be calculated as:
OS = (Vset + Vrst)/2
This offset term will contain the DC offset of both the sensor
bridge and interface electronics, as well as the temperature
drift of the bridge and interface electronics. Store this value
and subtract it from all future bridge output readings. Once
the bridge is RESET, it will remain in that state for years—
or until a disturbing field (>20 gauss) is applied. A timer can
be set, say every 10 minutes, to periodically update the
offset term. A flow chart is shown in Figure 14 along with a
timing diagram in Figure 15 to illustrate this process.
Figure 13—Set/Reset Pulse With Clock Control (1021/1022)
Figure 15—Single Clock Set/Reset Pulse Circuit (1021/1022)
Figure 14—Low Power Set/Rst Flowchart
SET Pulse
Read Vset
RESET Pulse
Read Vrst
OS = (Vset+Vrst)/2
Vout = Vrst - OS
Timer
expired?
Read Vrst
y
n
9,15
1µF (1)
+5 to 6V
14
HMC1022
Clock
S/R
1
2
4
3
5,6
7,8
(1) Tantalum, low R
(2) Rds ~0.2 ohm
200
8
set rst set
Clock
S/R
4 to14V
-4 to -14V
TPW ~ 2 µsec
5V
set
reset
IRF7105 (2)
DI9952 (2)
0.1µF
T
a
Reset
Set
S/R
Vp
-Vp
T
a > 5 µsec
T
b > 1 µsec
T
c > 20 µsec, 50 msec(max)
T
PW ~ 2 µsec
T
d > 20 µsec Vp > 3 V
T
PW
set
reset
T
b
T
a
T
c
read
Vset
read
Vrst
T
d
T
d
Vout
1µF (1)
+3.3 to
6.5V
Reset
NDS9933
2,4
1,3
5,6,7,8
(1) Tantalum, low R
(2) Rds ~0.2 ohm
Set
200
5,6,7,8
1,3
2,4
NDS8926
9,1514
HMC1022
S/R
8
0.1µF
+