Product Drawings

DxDESIGNER
SCALE:
DRAWING NO.SIZE REV
D
12
345
6
7
8
A
B
C
D
HONEYWELL INTERNATIONAL INC.
A
B
C
D
12
345
6
7
8
DRAWN BY
12/09/2018:13:41
NONE
CPO-PC200,CPO-PC400,CPO-PC400W
A
HOME & BUILDING TECHNOLOGIES
HONEYWELL CONFIDENTIAL
AND PROPRIETARY
M Back
23Jun2017
Number
SOM Board
@PRINTORDER=3
MMDC
VDD_ARM
VDD_SNVS
DDR_VREF
SDIO_4
V33
USB1_OTG
USB2_HST
UART_X5
I2C_1
I2C_2
SPI_2
SPI_5
CAN
SDIO_2
GPIO
PWM
ENET1
ENET2
JTAG
PCIE
INT_B
POR_B
VDD_EMMC
VDD_ENET
SDIO_3
BOOT0
PROCESSOR
DDR_ADDR[0:14]
DDR_SDBA[0:2]
DDR_DATA[0:7]
DDR_CTRL
DDR_DQM0
DDR_DQM1
DDR_SDQS0_N
DDR_SDQS0_P
DDR_SDQS1_N
DDR_SDQS1_P
DDR_VREF_CA
DDR_VREF_DQ
DDR_DATA[8:15]
I2C_1
MMDC
SDIO_4
ENET1
ENET2
I2C_2
SPI_5
USB1_OTG
USB2_HST
SDIO_2
SPI_2
VIN VDD_ARM
VDD_SNVS
E&ES COMMON CPU BOARD
Top Level Schematic - Block diagram
INT_B
DDR3L_256K_X16_1
PWM
CAN
DDR_ADDR[0:14]
DDR_SDBA[0:2]
DDR_DATA[0:7]
DDR_CTRL
DDR_DQM0
DDR_DQM1
DDR_SDQS0_N
DDR_SDQS0_P
DDR_SDQS1_N
DDR_SDQS1_P
DDR_VREF_CA
DDR_VREF_DQ
DDR_DATA[8:15]
DDR3L_256K_X16_2
UART_x5
GPIO
V33
PCIE
DAT[0:7]
POR_B
DDR_VREF_DQ1
DDR_VREF_CA1
USB1_OTG
USB2_HST
UART_x5
I2C_2
SPI_2
SPI_5
CAN
SDIO_2
GPIO
PWM
ENET2
PCIE
ENET1
SDIO_3
VIN
PWR_OFF_B
LDO3
LDO1
POR_B
BOOT0
SODIMM_CONNECTOR
DDR_ADDR[0:14]
DDR_CTRL
DDR_DATA[0:7]
DDR_SDBA[0:2]
DDR_DATA[16:23]
DDR_ADDR[0:14]
DDR_SDBA[0:2]
DDR_DATA[24:31]
DDR_CTRL
DDR_DATA[8:15]
DDR Byte lanes
swapped to
optimise layout
Byte
3
2
1
0
Order
2
3
1
0
DDR data lines
swapped to
optimise layout
Byte Order
0 D7
D6
D5
D4
D3
D2
D1
D0
1
2
Not
swapped
3
Not
swapped
DDR_VREF_CA2
VDD_ARM
VDD_SNVS
V33
I2C_1
INT_B
POR_B
VIN
LDO3
PWR_OFF_B
LDO1
LDO4
POWER
VDD_1P8
RST_B
CLK
CMD
DAT[0:7]
VDD_IO
EMMC_4GB_153
D15
D14
D13
D12
D11
D10
D9
D8
SDIO_3
PWR_OFF_B
1 2
Z1
1 2
Z2
1 2
Z3
DDR_VREF_DQ2
21
Z4
BOOT0