Product Drawings

DxDESIGNER
SCALE:
DRAWING NO.SIZE REV
D
12
345
6
7
8
A
B
C
D
HONEYWELL INTERNATIONAL INC.
A
B
C
D
12
345
6
7
8
DRAWN BY
CPO-PC200,CPO-PC400,CPO-PC400W
A
HOME & BUILDING TECHNOLOGIES
HONEYWELL CONFIDENTIAL
AND PROPRIETARY
M Back
25OCT2017
Number
SOM Board
12/09/2018:13:41
NONE
NC
NC
NC
NC
+1.35V
+1.35V
E&ES COMMON CPU
MEMORY - DDR3L 256k x16
DDR_ADDR[0:14]
DDR_CTRL
DDR_DATA[0:7]
DDR_DQM0
DDR_DQM1
DDR_SDBA[0:2]
DDR_SDQS0_N
DDR_SDQS0_P
DDR_SDQS1_N
DDR_SDQS1_P
DDR_SDQS1_P
DDR_SDQS1_N
DDR_SDQS0_P
DDR_SDQS0_N
DDR_SDBA[0:2]
DDR_ADDR[0:14]
DDR_CTRL
DDR_DATA[0:7]
Core supply
I/O Driver supply
U5
L8K1
C7
G3
M7
L9
L1
J9
H1
M8
M3
T2
T7
T9
T1
P9
P1
M9
J2
G1
G9
F9
E8
E2
D8
D1
B9
B1
H2
H9
F1
E9
R1
R9
N9
K8
N1
K2
T3
D7
J1
C8
C3
A3
B8
A2
A7
C2
E3
J8
G8
E1
B3
M1
A9
G7
D9
B2
D2
C9
C1
A8
A1
H7
G2
H8
H3
F8
F2
F7
B7
F3
L3
D3
E7
K7
J7
K9
L2
K3
J3
P8
N3
N8
M2
N7
R7
L7
R3
P7
P3
N2
P2
R8
R2
T8
A8
A7
A6
A5
A3
A2
A1
A9
A10/AP
A11
A12/BC
BA0
BA1
A0
A
0
33554431
A4
RAS
CAS
CS
CKE
[PWRDN/RFSH]
CK
CK
M1[LDM]
M2[UDM]
EN3[RD]
C4[WR]
LDQS
UDQS
[DQ1]
[DQ2]
[DQ3]
[DQ4]
[DQ5]
[DQ6]
[DQ7]
VDDQ
VDD
VSS
1(A,4D)
[DQ0]A,3
[DQ11]
[DQ12]
[DQ13]
[DQ14]
[DQ15]
[DQ9]
[DQ10]
NC
2(A,4D)
[DQ8]A,3
A13
VSSQ
A14
RESET
BA2
VREFCA
VREFDQ
NC
NC
NC
NC
LDQS
UDQS
ODT ZQ
DRAM 32MX16 8 BANKS
Do not share vias between the Core and I/O driver supplies,
or for VSS and VSSQ balls
Core supply decouplers to be placed at each corner
DDR_VREF_CA
DDR_VREF_DQ
C60
16V
10%
0.1uF 0.1uF
10%
16V
C61 C62
16V
10%
0.1uF 0.1uF
10%
16V
C63 C64
16V
10%
0.1uF 0.1uF
10%
16V
C65 C66
16V
10%
0.1uF 0.1uF
10%
16V
C67 C68
16V
10%
0.1uF
0.1uF
10%
16V
C69 C70
16V
10%
0.1uF
@PRINTORDER=10
DDR_DATA[8:15]
DDR_DATA[8:15]
UPPER
TP33TP34
MT41K256M16TW-107_IT
Route DDR_VREF_CA and DDR_VREF_DQ separately from where they
are generated.
Trace width of at least 0.025in and kept away from other noisy signals.
R34
62.5mW
1%
240
C37
16V
10%
0.22uF
C38
16V
10%
0.22uF
C39
16V
10%
0.22uF
C40
16V
10%
0.22uF