Product Specs

Page 30
nRF51802 Product Specification v1.2
4.9 Temperature sensor (TEMP)
The temperature sensor measures die temperature over the temperature range of the device with 0.25° C
resolution.
4.10 Serial Peripheral Interface (SPI/SPIS)
The SPI interfaces enable full duplex synchronous communication between devices. They support a three-
wire (SCK, MISO, MOSI) bi-directional bus with fast data transfers. The SPI Master can communicate with
multiple slaves using individual chip select signals for each of the slave devices attached to a bus. Control of
chip select signals is left to the application through use of GPIO signals. SPI Master has double buffered I/O
data. The SPI Slave includes EasyDMA for data transfer directly to and from RAM allowing Slave data
transfers to occur while the CPU is IDLE.
The GPIOs used for each SPI interface line can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of printed circuit
board space and signal routing.
The SPI peripheral supports SPI mode 0, 1, 2, and 3.
Table 13 SPI properties
4.10.1 Enable 4 Mbps SPIS bit rate
In order to utilize 4 Mbps bit rate for SPIS, the SPIS must be the only peripheral using a specific RAM section.
Construction of RAM sections are described in Section 3.2.2 “RAM organization” on page 17. If other
peripherals than SPIS use a specific RAM section, only 2 Mbps bit rate is possible.
4.11 Two-wire interface (TWI)
The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA). The
protocol makes it possible to interconnect up to 127 individually addressable devices. The interface is
capable of clock stretching, supporting data rates of 100 kbps and 400 kbps.
The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of board space
and signal routing.
Table 14 Two-wire properties
Instance Master/Slave
SPI0 Master
SPI1 Master
SPIS1 Slave
Instance Master/Slave
TWI0 Master
TWI1 Master