Product Specs

Page 41
nRF51802 Product Specification v1.2
Power on reset time (t
POR
) is the time from when the supply starts rising to when the device comes out of
reset and the CPU starts. The time increases with, and is inclusive of, supply rise time from 0 V to VDD.
Table 28 gives t
POR
for a number of supply rise times, simulated with a linear ramp from 0 V to VDD, over the
supply voltage range 1.8 V to 3.6 V.
Table 28 Power on reset time
The data in Figure 9 and Table 29 show measured t_
POR
data. Measurements were taken using the reference
circuit shown in Section 11.3.1 “QFAA QFN48 schematic with internal LDO setup” on page 73 with the given
supply voltage and temperature conditions.
Figure 9 Power on reset time (Test level 2)
Table 29 Supply rise time at sample voltages for the measured data shown in Figure 9.
Symbol Description Note Min. Typ. Max. Units
Test
level
t
POR, 10 μs
Power on reset time, 10 μs rise
time (0 V to VDD).
0.6 3.2 20 ms 1
t
POR, 1 ms
Power on reset time, 1 ms rise
time (0 V to VDD).
1.5 4.1 21 ms 1
t
POR, 10 ms
Power on reset time, 10 ms rise
time (0 V to VDD).
10 13 30 ms 1
t
POR, 50 ms
Power on reset time, 50 ms rise
time (0 V to VDD).
38 52 68 ms 1
VDD Rise Time from 10% to 90% of VDD
1.8 570 μs
3.0 605 μs
3.6 635 μs