technical reference guide april 2003 Compaq D315 and hp d325 Personal Computers This document provides information on the design, architecture, function, and capabilities of the Compaq D315 and the HP d325 Personal Computers. This information may be used by engineers, technicians, administrators, or anyone needing detailed information on the products covered.
This document is designed for printout in the 8 ½- x 11-inch format. The title block below may can be copied and/or cut out and placed into a slip or taped onto the binder.
Technical Reference Guide NOTICE © 2003 Hewlett-Packard Company HP, Hewlett-Packard, and the Hewlett-Packard logo are trademarks of the Hewlett-Packard Company in the U.S. and other countries. Compaq, the Compaq logo, and iPAQ are trademarks of Hewlett-Packard Development Company, L.P. in the U.S. and other countries. Microsoft, MS-DOS, Windows, Windows NT are trademarks of Microsoft Corporation in the United States and other countries.
Technical Reference Guide ii Compaq D315 and hp d325 Personal Computers Featuring the AMD Athlon XP Processor Second Edition –- April 2003
Technical Reference Guide TABLE OF CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................. 1.1 ABOUT THIS GUIDE ................................................................................................................ 1-1 1.1.1 ONLINE VIEWING............................................................................................................ 1-1 1.1.2 HARDCOPY ..........................................
Technical Reference Guide CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM............................................................................. 3.1 INTRODUCTION....................................................................................................................... 3-1 3.2 ATHLON XP PROCESSOR ....................................................................................................... 3-2 3.2.1 PROCESSOR OVERVIEW ..........................................................................
Technical Reference Guide CHAPTER 5 INPUT/OUTPUT INTERFACES.......................................................................................... 5.1 INTRODUCTION....................................................................................................................... 5-1 5.2 ENHANCED IDE INTERFACE ................................................................................................. 5-1 5.2.1 IDE PROGRAMMING ......................................................................
Technical Reference Guide CHAPTER 6 INTREGRATED GRAPHICS SUBSYSTEM...................................................................... 6.1 6.2 6.3 6.4 6.5 6.6 INTRODUCTION....................................................................................................................... 6-1 FUNCTIONAL DESCRIPTION................................................................................................. 6-2 DISPLAY MODES ...........................................................................
Technical Reference Guide APPENDIX A ERROR MESSAGES AND CODES............................................................................ A-1 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 A.16 A.17 A.18 A.19 A.20 INTRODUCTION...................................................................................................................... A-1 BEEP/KEYBOARD LED CODES.............................................................................................
Technical Reference Guide APPENDIX D COMPAQ/INTEL NETWORK INTERFACE CONTROLLER ADAPTERS .............. D.1 INTRODUCTION...................................................................................................................... D-1 D.2 FUNCTIONAL DESCRIPTION................................................................................................ D-2 D.2.1 AOL FUNCTION............................................................................................................... D-3 D.2.
Technical Reference Guide LIST OF FIGURES FIGURE 2-1. COMPAQ D315 AND HP D325 PERSONAL COMPUTERS ............................................................ 2-1 FIGURE 2-2. CABINET LAYOUT, FRONT VIEWS ........................................................................................... 2-4 FIGURE 2-3. CABINET LAYOUT , REAR VIEWS ............................................................................................ 2-5 FIGURE 2-4. CHASSIS LAYOUT, LEFT SIDE VIEW .................................
Technical Reference Guide FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM .......................................................C-2 FIGURE C–2. PS/2 KEYBOARD-TO-SYSTEM TRANSMISSION, TIMING DIAGRAM ........................................C-3 FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS ..........................................................C-5 FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS ...............................................................C-5 FIGURE C–5. U.S.
Technical Reference Guide LIST OF TABLES TABLE 1–1. ACRONYMS AND ABBREVIATIONS ........................................................................................... 1-5 TABLE 2-1. FEATURE DIFFERENCE MATRIX ................................................................................................. 2-2 TABLE 2-2. FEATURE DIFFERENCE MATRIX ................................................................................................. 2-8 TABLE 2-3. CHIPSET FUNCTIONS .............................
Technical Reference Guide TABLE 5–19. TABLE 5–20. TABLE 5–21. TABLE 5–22. TABLE 5–23. TABLE 5–24. TABLE 5–25. TABLE 5–26. TABLE 5–27. USB CONNECTOR PINOUT ................................................................................................... 5-25 USB CABLE LENGTH DATA ................................................................................................ 5-25 AC’97 AUDIO CONTROLLER PCI CONFIGURATION REGISTERS ...........................................
Technical Reference Guide Chapter 1 INTRODUCTION 1. Chapter 1 INTRODUCTION 1.1 ABOUT THIS GUIDE This guide provides technical information about Compaq D315 and the HP d325 personal computers, both which feature the AMD Athlon XP processor and an NVidia NForce series chipset. This document describes in detail the system’s design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.
Chapter 1 Introduction 1.2 ADDITIONAL INFORMATION SOURCES For more information on components mentioned in this guide refer to the indicated manufacturers’ documentation, which may be available at the following online sources: ♦ ♦ ♦ ♦ ♦ ♦ 1.3 Hewlett-Packard Company: http://www.hp.com Advanced Micro Devices, Inc: http://www.amd.com NVIDIA Corporation: http://www.nvidia.com Standard Microsystems Corporation: http://www.smsc.com Texas Instruments Inc.: http://www.ti.com USB user group: http://www.usb.
Technical Reference Guide 1.3.2 hp MODEL NUMBERING CONVENTION The model numbering convention for HP systems is as follows: dNNNsm/A2.
Chapter 1 Introduction 1.5.1 VALUES Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter “h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.” Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise stated. 1.5.2 RANGES Ranges or limits for a parameter are shown using the following methods: Example A: Example B: Bits <7..4> = bits 7, 6, 5, and 4.
Technical Reference Guide 1.6 COMMON ACRONYMS AND ABBREVIATIONS Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1–1. Acronyms and Abbreviations Table 1-1.
Chapter 1 Introduction Table 1-1.
Technical Reference Guide Table 1-1.
Chapter 1 Introduction Table 1-1.
Technical Reference Guide Table 1-1.
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Technical Reference Guide Chapter 2 SYSTEM OVERVIEW 2. Chapter 2 SYSTEM OVERVIEW 2.1 INTRODUCTION The Compaq D315 and HP d325 personal computers (Figure 2-1) deliver outstanding manageability, serviceability, and compatibility for enterprise environments. Based on the AMD Athlon XP processor and an NVidia NForce Chipset, these systems emphasize performance along with industry compatibility. These models feature an architecture incorporating the PCI bus.
Chapter 2 System Overview 2.2 FEATURES AND OPTIONS This section describes the standard features and available options. 2.2.1 STANDARD FEATURES The following standard features are included on all models: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ AMD Athlon XP processor Three full-height, full-length PCI slots One AGP slot 3.5 inch, 1.44-MB diskette drive IDE controller w/UATA/100 mode support 5 drive bays (two internal 3.5”, two internal 5.25”, one 3.
Technical Reference Guide 2.2.
Chapter 2 System Overview 2.3 MECHANICAL DESIGN The following subsections describe the mechanical (physical) aspects of the Compaq D315 PC and the HP Business PC d325 models. ! CAUTION: Voltages are present within the system unit whenever the unit is plugged into a live AC outlet, regardless of the system's “Power On” condition. Always disconnect the power cable from the power outlet and/or from the system unit before handling the system unit in any way.
Technical Reference Guide 2.3.1.2 Rear Views Figure 2-4 shows the rear view of the Compaq D315 and HP d325 systems.
Chapter 2 System Overview 2.3.2 CHASSIS LAYOUT This section describes the internal layout of the chassis. For detailed information on servicing the chassis refer to the multimedia training and/or the Service Reference Guide for these systems. Figure 2-4 shows the layout for the Compaq D315 or hp d325 personal computers.
Technical Reference Guide 2.3.3 BOARD LAYOUTS Figure 2-5 shows the system boards.
Chapter 2 System Overview 2.4 SYSTEM ARCHITECTURE The Compaq D315 and HP d325 feature an architecture based on the AMD Athlon XP processor and an NVidia NForce chipset (Figure 2-6). The AMD Athlon XP processor features an x86-class CPU that uses a highly-pipelined architecture to process a high volume of data per clock cycle to provide exceptional performance in handling audio, video, and image files. Operating at speeds up to 2.
Technical Reference Guide Athlon XP Processor FSB NForce Chipset Memory Bus North Bridge Monitor RGB GeForce MX Graphics AGP Slot AGP I/F Hyper Transport Link Bus Pri. IDE Bus ATA100 Hard Drive CD Audio Audio Subsystem Power Supply DDR SDRAM SDRAM Cntlr. Sec. IDE Bus Pri. IDE Cntlr. South Sec. IDE Bridge Cntlr. NIC Cntlr. USB Cntlrs.
Chapter 2 System Overview 2.4.1 AMD ATHLON XP PROCESSOR The systems covered in this guide feature the AMD Athlon XP processor. This processor is compatible with software written for most x86-type microprocessors including the AMD Duron and Intel Pentium-type processors and includes the following features: ♦ ♦ ♦ ♦ QuantiSpeedTM architecture 128-KB L1 and 256-KB L2 full-speed caches 3DNow!TM professional technology (full SSE compatibility) 0.
Technical Reference Guide 2.4.2 CHIPSET The D315 model uses a NVidia NForce 220 chipset while the D325 model uses the NVidia NForce2 chipset. Table 2-3 provides a comparison of the two chipset types. Table 2-3. Chipset Functions Table 2-3.
Chapter 2 System Overview 2.4.4 SYSTEM MEMORY These systems use the NVidia IGP component that supports DDR SDRAM. The system board provides two sockets that accept industry-standard unbuffered DDR DIMMs. The D315 system uses the IGP-64 controller that supports 64-bit PC2100 DDR memory and a maximum of 1 gigabyte of memory. The d325 system uses the IGP-128 controller supporting 128-bit (when two DIMMs are installed) PC2700 DDR memory and a maximum of 2 gigabytes of memory. 2.4.
Technical Reference Guide 2.4.8 NETWORK INTERFACE CONTROLLER All models feature a Network Interface Controller (NIC). The D315 model includes either a Accton 10/100 NIC featuring Wake-On-LAN or an Intel 10/100 NIC PCI card featuring WOL and AOL, depending on configuration. The d325 model features a 3Com NIC integrated on the system board. 2.4.9 GRAPHICS SUBSYSTEM The IGP component provides AGP interface support as well as including a GeForce MX-class graphics processing unit.
Chapter 2 System Overview 2.4.10 AUDIO SUBSYSTEM This system uses the integrated AC97 audio controller of the chipset and the Analog Devices AD1885 (D315 models) or AD1981 (d325 models) codec. These systems include microphone and line inputs and headphone and line outputs. The system includes a 3-watt output amplifier driving an internal speaker, and the headphone and microphone jacks are duplicated on both the front panel and the rear chassis panel. 2.
Technical Reference Guide Table 2-8. Physical Specifications Table 2-8. Physical Specifications Height Width Depth Weight (nom.) [1] Maximum Supported Weight [2] 14.50 in (36.83 cm) 6.88 in (17.48 cm) 16.55 in (42.04 cm) 23.8 lb (10.92 kg) 100 lb (45.50 kg) NOTES: [1] System weight may vary depending on installed drives/peripherals. [2] Assumes reasonable article(s) such as a display monitor and/or another system unit. Table 2-9. Diskette Drive Specifications Table 2-9.
Chapter 2 System Overview Table 2-10. Optical Drive Specifications Table 2-10. Optical Drive Specifications Parameter Part number Interface Type Media Type (reading) Media Type (writing) Transfer Rate (Reads) 48x CD-ROM 232320-001 IDE Mode 1,2, Mixed Mode, CD-DA, Photo CD, Cdi, CD-XA N/a 4.
Technical Reference Guide Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM 3. Chapter 3 PROCESSOR/MEMORY SUBSYSTEM 3.1 INTRODUCTION This chapter describes the processor/memory subsystem. These systems feature the AMD Athlon XP processor and an NVidia NForce chipset (Figure 3-1). Athlon XP Processor 64-Bit FSB Cntl System Memory FSB I/F Memory Bus [1] GPU IGP AGP I/F Memory Cntlr. XMM1 XMM2 DIMM In Socket DIMM Socket HT I/F Covered in chapter 6.
Chapter 3 Processor/Memory Subsystem 3.2 ATHLON XP PROCESSOR This system features an AMD Athlon XP processor in a Socket 462-compatible package mounted with a passive heat sink. The mounting socket allows the processor to be easily changed for servicing and/or upgrading. 3.2.1 PROCESSOR OVERVIEW The AMD Athlon XP processor represents the latest development of AMD processors that takes advantage of the Windows XP operating system.
Technical Reference Guide Figure 3-2 illustrates the internal architecture of the Athlon XP processor.
Chapter 3 Processor/Memory Subsystem The AMD Athlon XP processor is compatible with software written for Athlon 4, Duron, and most other x86 processors, but will require the latest versions of operating system software to take advantage of the specific features and functions. 3.2.2 PROCESSOR UPGRADING This system uses the Socket A mounting socket. A replacement processor must use the same type heat sink (passive or fan cooled) as the original to ensure proper cooling.
Technical Reference Guide 3.3 MEMORY SUBSYSTEM These systems provide two 184-pin DIMM sockets that accept DDR DIMMs. The D315 models ship with PC2100 DIMMs while the d325 models ship with PC2700 DIMMs. NOTE: The DDR SDRAM DIMM "PCxxxx" reference designates bus bandwidth (i.e., a PC2100 DIMM, operating at a 266-MHz effective speed, provides a throughput of 2100 MBps (8 bytes × 266 MHz)). These systems support DIMMs with the following specifications: ♦ ♦ ♦ Unbuffered, non-ECC with SPD rev. 1.
Chapter 3 Processor/Memory Subsystem The SPD address map is shown below. Table 3–1. SPD Address Map (SDRAM DIMM) Table 3-1. SPD Address Map (SDRAM DIMM) Byte 0 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NOTES: Description No. of Bytes Written Into EEPROM Total Bytes (#) In EEPROM Memory Type No. of Row Addresses On DIMM No. of Column Addresses On DIMM No.
Technical Reference Guide Figure 3-3 shows the system memory map. FFFF FFFFh FFE0 0000h FFDF FFFFh FEC1 0000h FEC0 FFFFh FEC0 0000h FEBF FFFFh High BIOS Area (2 MB) 4 GB PCI Memory (18 MB) APIC Config.
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Technical Reference Guide Chapter 4 SYSTEM SUPPORT 4. Chapter 4 SYSTEM SUPPORT 4.1 INTRODUCTION This chapter covers subjects dealing with basic system architecture and covers the following topics: ♦ ♦ ♦ ♦ ♦ ♦ ♦ PCI bus overview (4.2) AGP bus overview (4.3) System resources (4.4) System clock distribution (4.5) Real-time clock and configuration memory (4.6) System management (4.7) Register map and miscellaneous functions (4.
Chapter 4 System Support 4.2 PCI BUS OVERVIEW NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2. These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles address/data transfers through the identification of devices and functions on the bus.
Technical Reference Guide 4.2.1 PCI BUS TRANSACTIONS The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle.
Chapter 4 System Support Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream PCI bus as identified by bus number bits <23..16>. Figure 4-2 shows the configuration cycle format and how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..
Technical Reference Guide The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header. 31 24 23 16 15 8 7 0 Register Index 31 24 23 16 15 8 7 0 FCh Device-Specific Area Device-Specific Area Min. Lat. Min. GNT Int. Pin Int.
Chapter 4 System Support 4.2.2 PCI BUS MASTER ARBITRATION The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus.
Technical Reference Guide 4.2.3 OPTION ROM MAPPING During POST, the PCI bus is scanned for devices that contain their own specific firmware in ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3). 4.2.4 PCI INTERRUPTS Eight interrupt signals (INTA- thru INTD-) are available for use by PCI devices. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots.
Chapter 4 System Support 4.2.7 PCI CONNECTOR B94 B62 A62 A94 B52 A52 B1 B49 A1 A49 Figure 4-4. PCI Bus Connector (32-Bit Type) Table 4-3. PCI Bus Connector Pinout Table 4-3. PCI Bus Connector Pinout Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 — B Signal -12 VDC TCK GND TDO +5 VDC +5 VDC INTBINTDPRSNT1RSVD PRSNT2GND GND RSVD GND CLK GND REQ+5 VDC AD31 AD29 GND AD27 AD25 +3.3 VDC C/BE3AD23 GND AD21 AD19 +3.
Technical Reference Guide 4.3 AGP BUS OVERVIEW NOTE: For a detailed description of AGP bus operations refer to the AGP Interface Specification Rev. 2.0 available at the following AGP forum web site: http://www.agpforum.org/index.htm The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations.
Chapter 4 System Support 4.3.1.1 Data Request Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA lines (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers.
Technical Reference Guide AGP 2X Transfers During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 46). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes (DnB) are latched on the rising edge of AD_STBx.
Chapter 4 System Support AGP 8X Transfers The AGP 8X transfer rate (supported on d325 models only) allows 32 bytes of data to be transferred in one clock cycle. As with the other transfer rates the 66-MHz CLK signal is used only for qualifying control signals while strobe signals are used to latch each 4-byte transfer on the AD lines. As shown in Figure 4-8, 4-byte block DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of AD_STBx-.
Technical Reference Guide 4.3.2 AGP CONNECTOR Figure 4-8 shows the system’s keyed AGP connector that accepts only 1.5-volt AGP adapters. The pin out is listed in Table 4-4. B94 A94 A1 B1 A41 A46 B41 B46 A66 B66 Figure 4-9. AGP Bus Connector Table 4-4. AGP Bus Connector Pinout Table 4-4.
Chapter 4 System Support 4.4 SYSTEM RESOURCES This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants. 4.4.1 INTERRUPTS The microprocessor uses two types of hardware interrupts; maskable and nonmaskable.
Technical Reference Guide 8259 Mode The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259equivalent logic. Table 4-5 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first. Table 4-5. Maskable Interrupt Priorities and Assignments Table 4-5.
Chapter 4 System Support The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the standard ISA interrupts (IRQn). NOTE: The APIC mode is supported by the Windows NT, Windows 2000, and Windows XP operating systems. Systems running the Windows 95 or 98 operating system will need to run in 8259 mode. Maskable interrupt processing is controlled and monitored through standard AT-type I/O-mapped registers. These registers are listed in Table 4-6. Table 4-6.
Technical Reference Guide The NMI Status Register at I/O port 061h contains NMI source and status data as follows: NMI Status Register 61h Bit 7 6 5 4 3 2 1 0 Function NMI Status: 0 = No NMI from system board parity error.
Chapter 4 System Support 4.4.2 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks. NOTE: This section describes DMA in general.
Technical Reference Guide The DMA logic is accessed through two types of I/O mapped registers; page registers and controller registers. 4.4.2.1 DMA Page Registers The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit) address for the DMA channels. Table 4-8 lists the page register port addresses. Table 4-8. DMA Page Register Addresses Table 4-8.
Chapter 4 System Support DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only possible between 16-bit memory and 16-bit peripherals. The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus.
Technical Reference Guide 4.5 SYSTEM CLOCK DISTRIBUTION This system uses clock synthesizers in the IGP and the MCP or MCP-2 components. A 14.31818MHz crystal provides an input for clock circuits of the MCP. Table 4-10 lists clock signals that are distributed between system board components. Frequencies that are used only internally in chips and components are not listed. Table 4-10. Clock Generation and Distribution Table 4-10.
Chapter 4 System Support 4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the MCP component and is MC146818-compatible. As shown in the following figure, the MCP component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area.
Technical Reference Guide 4.6.2 CMOS ARCHIVE AND RESTORE During the boot process the BIOS saves a copy of CMOS to the flash ROM. If the system becomes unusable, the last good copy of CMOS can be recalled using the power-override function as follows: 1. 2. 3. With the unit powered down, press and release the power button to initiate the boot sequence. Immediately after releasing the power button, press it again and hold (typically at least four seconds) until the unit powers off again.
Chapter 4 System Support 4.7 SYSTEM MANAGEMENT This section describes functions having to do with security, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally configured through the Setup utility. 4.7.1 SECURITY FUNCTIONS This system includes various features that provide different levels of security.
Technical Reference Guide 4.7.1.3 Cable Lock Provision These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock mechanism. 4.7.1.4 I/O Interface Security The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup utility to guard against unauthorized access to a system. In addition, the ability to write to or boot from a removable media drive (such as the diskette drive) may be enabled through the Setup utility.
Chapter 4 System Support 4.7.2 POWER MANAGEMENT This system provides baseline hardware support of ACPI- and APM-compliant firmware and software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be placed into a reduced power mode either automatically or by user control. The system can then be brought back up (“wake-up”) by events defined by the ACPI specification.
Technical Reference Guide Table 4-13. System Operational Status LED Indication Table 4-13. System Operational Status LED Indications D315 d325 System Status Power LED Power LED S0: System on (normal operation) Steady green Steady green S1: Suspend Blinks green @ .5 Hz Blinks green @ .5 Hz S3: Suspend to RAM Blinks green @ .5 Hz Blinks green @ .
Chapter 4 System Support 4.7.4.1 Cooling for D315 Models The temperature controller produces the Fan CMD (which varies from 0 to +2.5 VDC) that is applied to the speed control circuitry of the power supply assembly. The output of the speed control circuitry controls the power supply assembly’s internal fan and is also routed back to the system board and, in the default jumper configuration, is applied as the Fan Sink signal to the negative terminal of the connected fans.
Technical Reference Guide 4.7.4.2 Cooling for d325 Models The fan control logic on the d325 model differs from the D315 system in that fans are controlled by the system board logic. The fans are driven by a constant positive 12 volts on one side and a negative voltage that is variable through the Fan Cntrl logic. A Hardware Monitor ASIC monitors the temperature of the processor and changes the duty cycle of the Fan PWM to increase or decrease fan speed based on the processor temperature.
Chapter 4 System Support 4.8 REGISTER MAP AND MISCELLANEOUS FUNCTIONS This section contains the system I/O map and information on general-purpose functions of the MCP and I/O controller. 4.8.1 SYSTEM I/O MAP Table 4-14 lists the fixed addresses of the input/output (I/O) ports. Table 4-14. System I/O Map Table 4-14. System I/O Map I/O Port Function 0000..001Fh DMA Controller 1 0020..002Dh Interrupt Controller 1 002E, 002Fh Index, Data Ports to LPC47B367 I/O Controller (primary) 0030..
Technical Reference Guide 4.8.2 LPC47B367 I/O CONTROLLER FUNCTIONS The LPC47B367 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions uses indexed ports unique to the LPC47B367.
Chapter 4 System Support The systems covered in this guide utilize the following specialized functions built into the LPC47B367 I/O Controller: ♦ Power/HD LED status indicators – The I/O controller provides color and blink control for the front panel LEDs used for indicating system events as listed below. Indications valid for both D315 and d325 unless otherwise indicated. System Status Power LED HD LED S0: System on (normal operation) Steady green Green w/HD activity S1: Suspend Blinks green @ 0.
Technical Reference Guide Chapter 5 INPUT/OUTPUT INTERFACES 5. Chapter 5 INPUT/OUTPUT INTERFACES 5.1 INTRODUCTION This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 5.2 Enhanced IDE interface (5.2) Diskette drive interface (5.3) Serial interfaces (5.4) Parallel interface (5.
Chapter 5 Input/Output Interfaces 5.2.1.1 IDE Configuration Registers The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #9, function #0) are listed in Table 5-1. Table 5–1. IDE PCI Configuration Registers Table 5-1. IDE PCI Configuration Registers (MCP, Device 9/Function 0) PCI Conf. Addr.
Technical Reference Guide 5.2.2 IDE CONNECTOR This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive. Note that some signals are re-defined for UATA/33 and higher modes, which require a special 80-conductor cable (supplied) designed to reduce cross-talk. Device power is supplied through a separate connector. Figure 5-1. 40-Pin Primary IDE Connector (on system board). Table 5–3. 40-Pin Primary IDE Connector Pinout Table 5-3.
Chapter 5 Input/Output Interfaces 5.3 DISKETTE DRIVE INTERFACE The diskette drive interface supports up to two diskette drives, each of which use a common cable connected to a standard 34-pin diskette drive connector. Models that come standard with a 3.5inch 1.44-MB diskette drive will have the diskette drive installed as drive A. The drive designation is determined by which connector is used on the diskette drive cable.
Technical Reference Guide 5.3.1 DISKETTE DRIVE PROGRAMMING Programming the diskette drive interface consists of configuration, which occurs typically during POST, and control, which occurs at runtime. 5.3.1.1 Diskette Drive Interface Configuration The diskette drive controller must be configured for a specific address and also must be enabled before it can be used.
Chapter 5 Input/Output Interfaces Table 5–5. Diskette Drive Interface Control Registers Table 5-5. Diskette Drive Interface Control Registers Pri. Addr. 3F0h Sec. Addr.
Technical Reference Guide 5.3.2 DISKETTE DRIVE CONNECTOR This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-6 for the pinout) for diskette drives. Drive power is supplied through a separate connector. 2 1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Figure 5-2. 34-Pin Diskette Drive Connector. Table 5–6. 34-Pin Diskette Drive Connector Pinout Table 5-6.
Chapter 5 Input/Output Interfaces 5.4 SERIAL INTERFACE All models include at least one RS-232-C type serial interface to transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the LPC47B367 I/O controller component that includes two NS16C550-compatible UARTs. The UART supports the standard baud rates up through 115200, and also special high speed rates of 239400 and 460800 baud.
Technical Reference Guide 5.4.2 SERIAL INTERFACE PROGRAMMING Programming the serial interfaces consists of configuration, which occurs during POST, and control, which occurs during runtime. 5.4.2.1 Serial Interface Configuration The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also must be activated before it can be used. Address selection and activation of the serial interface are affected through the PnP configuration registers of the LPC47B367 I/O controller.
Chapter 5 Input/Output Interfaces 5.4.2.2 Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be directly controlled by software through the I/O-mapped registers listed in Table 5-9. Table 5–9. Serial Interface Control Registers Table 5-9. Serial Interface Control Registers COM1 Addr. 3F8h COM2 Addr.
Technical Reference Guide 5.5 PARALLEL INTERFACE All models include a parallel interface for connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into the LPC47B367 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
Chapter 5 Input/Output Interfaces 5.5.2 ENHANCED PARALLEL PORT MODE In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used.
Technical Reference Guide 5.5.4 PARALLEL INTERFACE PROGRAMMING Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime. 5.5.4.1 Parallel Interface Configuration The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account.
Chapter 5 Input/Output Interfaces 5.5.4.2 Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP).
Technical Reference Guide 5.5.5 PARALLEL INTERFACE CONNECTOR Figure 5-4 and Table 5-12 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port’s operational mode. 13 12 11 25 10 24 23 9 22 8 21 20 7 6 19 5 18 4 17 3 2 16 15 1 14 Figure 5-4. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5–12. DB-25 Parallel Connector Pinout Table 5-12.
Chapter 5 Input/Output Interfaces 5.6 KEYBOARD/POINTING DEVICE INTERFACE The keyboard/pointing device interface function is provided by the LPC47B367 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers.
Technical Reference Guide Control of the data and clock signals is shared by the 8042 and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard. After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042. Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5–13.
Chapter 5 Input/Output Interfaces 5.6.2 POINTING DEVICE INTERFACE OPERATION The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the IRQ12 interrupt. 5.6.
Technical Reference Guide 5.6.3.2 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes).
Chapter 5 Input/Output Interfaces Table 5-15 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU. Table 5–15. CPU Commands To The 8042 Table 5-15. CPU Commands To The 8042 Value 20h 60h A4h A5h A6h A7h A8h A9h AAh ABh ADh AEh C0h C2h C3h D0h D1h D2h D3h D4h E0h F0hFFh Command Description Put current command byte in port 60h. Load new command byte. Test password installed.
Technical Reference Guide 5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR These systems provide separate PS/2 connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-6 and Table 5-16 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5-6. Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis) Table 5–16. Keyboard/Pointing Device Connector Pinout Table 5-16.
Chapter 5 Input/Output Interfaces 5.7 UNIVERSAL SERIAL BUS INTERFACE The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems. All models provide six USB ports; four rear-mounted ports and two ports accessible in the front.
Technical Reference Guide 5.7.1 USB DATA FORMATS The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a 1 is represented by no change (between bit times) in signal level and a 0 is represented by a change in signal level.
Chapter 5 Input/Output Interfaces 5.7.2 USB PROGRAMMING Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime. 5.7.2.1 USB Configuration Each USB controller functions as a PCI device within the MCP component and is configured using PCI Configuration Registers as listed in Table 5-17. Table 5–17. USB Interface Configuration Registers Table 5-17. USB Interface Configuration Registers PCI Config. Addr.
Technical Reference Guide 5.7.3 USB CONNECTOR These systems provide type-A USB ports as shown in Figure 5-9 below. 1 3 2 4 Figure 5-9. Universal Serial Bus Connector Table 5–19. USB Connector Pinout Table 5-19. USB Connector Pinout Pin 1 2 Signal Vcc USB- Description +5 VDC Data (minus) Pin 3 4 Signal USB+ GND Description Data (plus) Ground 5.7.
Chapter 5 Input/Output Interfaces 5.8 AUDIO SUBSYSTEM This system includes an embedded Sound Blaster-compatible audio subsystem with front panelaccessible headphone and microphone jacks. 5.8.1 FUNCTIONAL ANALYSIS A block diagram of the audio subsystem is shown in Figure 5-10.
Technical Reference Guide PC Beep Audio MCP or MCP-2 PCI Bus Line In AC’97 Audio Cntlr. AC97 Link Bus (L) (R) Mic In L+R (Mono) Audio + TDA 7056 - Header Front Panel Assembly HP Out Audio (L/R) CD Audio (L) CD ROM Internal Speaker (L) (R) Audio Codec Headphones/ Line Out CD Audio (R) Switch Logic Audio Bias Panel En Audio Bias Mic In (L) Line Out (R) L+R Audio Figure 5-10.
Chapter 5 Input/Output Interfaces 5.8.2 AC97 AUDIO CONTROLLER The AC97 Audio Controller is a PCI device (device 6/function 0) that is integrated into the MCP component and supports the following functions: ♦ ♦ ♦ ♦ ♦ ♦ Read/write access to audio codec registers 16-bit stereo PCM output @ up to 48 KHz sampling 16-bit stereo PCM input @ up to 48 KHz sampling Acoustic echo correction for microphone AC’97 Link Bus ACPI power management 5.8.
Technical Reference Guide 5.8.4 AUDIO CODEC The audio codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-12, analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC).
Chapter 5 Input/Output Interfaces Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime. 5.8.5.1 Audio Configuration The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the MCP. Table 5-21 lists the key PCI configuration registers of the audio subsystem. Table 5–21. AC’97 Audio Controller PCI Configuration Registers Table 5-21.
Technical Reference Guide 5.8.6 AUDIO SPECIFICATIONS The specifications for the integrated AC’97 audio subsystem are listed in Table 5-23. The specifications listed are applicable to both D315 and d325 systems. Table 5–23. Audio Subsystem Specifications Table 5-23.
Chapter 5 Input/Output Interfaces 5.9 NETWORK INTERFACE CONTROLLER The HP d325 system includes a 10/100 Mbps network interface controller (NIC) consisting of a 82562-equivalent controller integrated into the 82801 ICH component coupled with a physical interface (PHY) component and an RJ-45 jack with integral status LEDs (Figure 5-13). The support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or fullduplex modes, and provides auto-negotiation of both mode and speed.
Technical Reference Guide NOTE: For the WOL and AOL features to function as described in the following paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with the strip turned off, disable WOL and AOL functionality. 5.9.
Chapter 5 Input/Output Interfaces 5.9.3 POWER MANAGEMENT SUPPORT The NIC features Wired-for-Management (WfM) support providing system wake up from network events (WOL) as well as generating system status messages (AOL) and supports both APM and ACPI power management environments. The controller receives 3.3 VDC (auxiliary) power as long as the system is plugged into a live AC receptacle, allowing support of wake-up events occuring over a network while the system is powered down or in a low-power state. 5.
Technical Reference Guide 5.9.4 NIC PROGRAMMING Programming the NIC consists of configuration, which occurs during POST, and control, which occurs at runtime. 5.9.4.1 Configuration The network interface function is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in the following table: Table 5–25. NIC Controller PCI Configuration Registers Table 5-25.
Chapter 5 Input/Output Interfaces 5.9.5 NIC CONNECTOR Figure 5-14 shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly. Activity LED Speed LED Pin 1 2 3 6 Description Transmit+ TransmitReceive+ Receive- 8 7 6 5 4 3 2 1 Figure 5-14. Ethernet TPE Connector (RJ-45, viewed from card edge) 5.9.6 NIC SPECIFICATIONS Table 5–27. 82559 NIC Operating Specifications Table 5-27.
Technical Reference Guide Chapter 6 INTEGRATED GRAPHICS SUBSYSTEM 6. Chapter 6 Intregrated Graphics Subsystem 6.1 INTRODUCTION This chapter describes graphics subsystem that is integrated into the IGP component on the system board. This graphics subsystem employs the use of system memory to provide efficient, economical 2D and 3D performance. Upgrading these systems is accomplished by installing a separate AGP graphics card in the AGP slot.
Chapter 6 Integrated Graphics Subsystem 6.2 FUNCTIONAL DESCRIPTION The NVidia NForce 220 chipset includes a graphics processing unit (GPU) integrated into the integrated graphics processor (IGP) component (Figure 6-1). The graphics controller can directly drive an external, analog multi-scan monitor at resolutions up to and including 1920 x 1440 pixels. The GPU includes a memory management feature that allocates portions of system memory for use as the frame buffer and for storing textures and 3D effects.
Technical Reference Guide Figure 6-2 shows the block diagram of the graphics processing unit. The GPU includes 256-bit 2D and 3D engines that work with a multi-pipelined processor. The processor provides hardwareassisted MPEG-2 decoding for DVD and HDTV video playback in resolutions up to 1280 x 720.
Chapter 6 Integrated Graphics Subsystem 6.3 DISPLAY MODES The GPU supports the following 2D display modes based on the 64-bit support of system memory: Table 6-1. 845G-Based Graphics Display Modes Table 6-1.
Technical Reference Guide 6.4 PROGRAMMING The IGP’s integrated graphics processing unit is configured using PCI configuration registers listed in Table 6-2. Table 6-2. 815E-Based Graphics Controller PCI Configuration Registers Table 6-2. Graphics Processing Unit PCI Configuration Registers (Device 0, Function 0, Bus 1) PCI Config. Addr.
Chapter 6 Integrated Graphics Subsystem 6.6 VGA MONITOR CONNECTOR The D315 model provides a standard VGA connector (Figure 6-3) for attaching an analog video monitor. The D325 model provides two VGA connectors. 5 10 2 3 4 99 15 14 13 8 1 7 12 6 11 Figure 6-3. VGA Monitor Connector, (Female DB-15, as viewed from rear). Table 6-3. DB-15 Monitor Connector Pinout Table 6-3.
Technical Reference Guide Chapter 7 POWER and SIGNAL DISTRIBUTION 7. Chapter 7 POWER SUPPLY AND DISTRIBUTION 7.1 INTRODUCTION This chapter describes the power supply and method of general power and signal distribution. Topics covered in this chapter include: ♦ ♦ ♦ 7.2 Power supply assembly/control (7.2) Power distribution (7.3) Signal distribution (7.
Chapter 7 Power and Signal Distribution 7.2.1 POWER SUPPLY ASSEMBLY The D315 models use a 220-watt power supply assembly with the specifications listed in the following table: Table 7-1. 220-Watt Power Supply Assembly Specifications Table 7-1. 220-Watt Power Supply Assembly Specifications Range/ Tolerance Min. Current Loading [1] Max. Current Surge Current [2] Input Line Voltage: 115VAC setting 90 - 132 VAC ---230VAC setting 180 - 264 VAC Line Frequency 47 - 63 Hz ---Constant Input (AC) Current --6.
Technical Reference Guide 7.2.2 POWER CONTROL The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When PS On is de-asserted, the Power Supply Assembly is off and all voltages (except +5 AUX) are not generated. Note that the +5 AUX voltage is always produced as long as the system is connected to a live AC source. 7.2.2.
Chapter 7 Power and Signal Distribution 7.2.2.2 Wake Up Events The PS On signal can be activated with a power “wake-up” of the system due to the occurrence of a magic packet, serial port ring, or PCI power management (PME) event. These events can be individually enabled through the Setup utility to wake up the system from a sleep (low power) state. NOTE: Wake-up functionality requires that certain circuits receive auxiliary power while the system is turned off.
Technical Reference Guide 7.2.3 POWER MANAGEMENT These systems include power management functions designed to conserve energy. These functions are provided by a combination of hardware, firmware (BIOS) and software. The system provides the following power management features: J ACPI v1.0b compliant (ACPI modes C1, C2, S1, and S3, ) J API 1.2 compliant (D315 only) J U.S. EPA Energy Star compliant Table 7-2 shows the comparison in power states. Table 7-3. System Power States Table 7-2.
Chapter 7 Power and Signal Distribution 7.3 POWER DISTRIBUTION 7.3.1 3.3/5/12 VDC DISTRIBUTION The power supply assembly includes a multi-connector cable assembly that routes DC power to the system board as well as to the individual drive assemblies. Figure 7-2 shows the power supply cabling for D315 models while figure 7-3 shows the power supply cabling for the d325 model. P2 P8 P6 P7 P4 P5 P7, P8 To Drive Assemblies 4 3 2 P2, P4-6 1 2 3 4 P9 P3 P9 P3 1 Power Supply Assembly (Assy.
Technical Reference Guide Figure 7-3 shows the power supply cabling for the d325 model. P2 P10 P4, P5 P8 P6 P7 P4 P5 To Drive Assemblies P7, P8 1 2 3 4 5 4 3 2 P2, P4-6, P10 1 2 3 4 P9 P3 P9 P3 Power Supply Assembly (Assy. #308437) To System Board P1 1 1 2 2 1 4 3 P1 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 Conn. P1 P1 [1] P4, 5 P6, 10 P3 P7, 8 P9 Pin 1 +3.3 +3.3 +3.3 +12 GND +5 NC Pin 2 +3.3 -12 RTN GND GND GND FC Pin 3 RTN RTN +5 GND +12.
Chapter 7 Power and Signal Distribution 7.3.2 LOW VOLTAGE PRODUCTION/DISTRIBUTION Voltages less than 3.3 VDC including processor core (VCore) voltage are produced through regulator circuitry (Figure 7-4) on the system board. +5 AUX 3.3 Auxiliary Circuit 3.3 AUX [1] 3.3 AUX 3.3 AUX Power Supply +3.3 VDC 1.2 Auxiliary Circuit DDR S3 PWR Circuit 1.5 / 1.4 Regulator Circuit +1.3 VDC DDR DIMMs +1.4 VDC Chipset PWM A +12.8 VDC VID3 2.6 VDC +12 VDC +5 VDC Processor Chipset +1.5 VDC +12.
Technical Reference Guide 7.4 SIGNAL DISTRIBUTION Figure 7-5 shows general signal distribution between the main subassemblies of the system units. Chassis Fan CPU Fan PCI NIC Card Serial Conn. PCI Bus PCI Slot Fan PWR SYS FAN Conn. Fan PWR CPU FAN Conn. TX Data, RX Data F_P Conn. JRW1 Conn. PWR_FAN Conn. Pri. IDE Conn. Sec. IDE Conn. CD1 Conn. FDD1 Conn. Mouse Kybd. Conn. HD Activity Pwr Btn, Pwr/HD LED 12.8 Vcpu 3/5/12 VDC, 5AUX PS On Fan CMD Audio 1 Conn. USB 4/5 Conn.
Chapter 7 Power and Signal Distribution Power Button/LED (F_P) Header HD LED Cathode 1 HD LED Anode 3 2 PS LED cathode 4 PS LED anode GND 5 M Reset 7 6 PWR Btn 8 GND +5 VDC 9 NC 11 10 Chassis ID0 GND 13 NC 15 Chassis ID1 17 12 GND 16 +5 VDC 18 GND Front Panel Audio (Audio 1) Header Mic Audio 1 2 GND Mic Bias 3 4 Vdd HP R 5 Option Det 7 HP L 9 6 HP BK R 10 HP BK L Front Panel USB (USB 4/5) Header Vcc 1 USB A - 3 USB A + 5 Option Det 7 2 Vcc 4 USB B 6 USB B + 8 GND 10 NC CD ROM Audio (CD1)Hea
Technical Reference Guide Chapter 8 SYSTEM BIOS 8. Chapter 8 SYSTEM BIOS 8.1 INTRODUCTION The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The ROM includes such functions as Power-On Self Test (POST), VGA BIOS, PCI device initialization, Plug ‘n Play support, ACPI power management activities, and the Setup utility.
Chapter 8 System BIOS 8.2 ROM FLASHING/UPGRADING The system BIOS firmware is contained in a flash ROM device that can be re-written with BIOS code (using the ROMPaq utility or a remote flash program) allowing easy upgrading, including changing the splash screen displayed during the POST routine. Upgrading the BIOS is not normally required but may be necessary if changes are made to the unit’s operating system, hard drive, or processor. All BIOS ROM upgrades are available directly from Hewlett-Packard.
Technical Reference Guide 8.3 BOOT FUNCTIONS The BIOS supports various functions related to the boot process, including those that occur during the Power On Self-Test (POST) routine. 8.3.1 BOOT DEVICE ORDER The default boot device order is as follows: 1. 2. 3. 4. 5. 6.
Chapter 8 System BIOS 8.3.3 MEMORY DETECTION AND CONFIGURATION This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus to obtain data on the following DIMM parameters: ♦ ♦ ♦ ♦ ♦ Presence Size Type Timing/CAS latency Memory speed NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific to this system.
Technical Reference Guide 8.4 SETUP UTILITY The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the F10 key is pressed during the time the F10 prompt is displayed in the lower right-hand corner of the screen during the POST routine. Highlights of the Setup utility are described in the following table.
Chapter 8 System BIOS Table 8-3. Setup Utility Functions Continued Heading Option Description Storage (continued) Device Configuration (continued) Translation Mode (IDE disks only) Lets you select the translation mode to be used for the device. This enables the BIOS to access disks partitioned and formatted on other systems and may be necessary for users of older versions of Unix (e.g., SCO Unix version 3.2). Options are Bit-Shift, LBA Assisted, User, and None.
Technical Reference Guide Table 8-3. Setup Utility Functions Heading Storage (continued) Option DPS Self-Test Description Allows user to execute self-tests on IDE hard drives capable of performing the Drive Protection System (DPS) self-tests.
Chapter 8 System BIOS Table 8-3. Setup Utility Functions Heading Security (continued) Continued Option Device Security Description Enables/disables serial, parallel, and USB ports, system audio, and network controller. Network Service Boot Enables/disables the computer’s ability to boot from an operating system installed on a network server. (Feature available on NIC models only; the network controller must reside on the PCI bus or be embedded on the system board.
Technical Reference Guide Table 8-3.
Chapter 8 System BIOS Table 8-3. Setup Utility Functions Heading Advanced (continued) Continued Option Bus Options Device Options PCI VGA Configuration Description Allows user to enable or disable: PCI bus mastering, which allows a PCI device to take control of the PCI bus PCI SERR# Generation.
Technical Reference Guide 8.5 CLIENT MANAGEMENT FUNCTIONS Table 8-4 is a partial list of the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaq-specific unless otherwise indicated. Table 8-4. Client Management Functions (INT15) Table 8-4.
Chapter 8 System BIOS To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC locations. The Windows NT extension table is as follows: ; Extension to BIOS SERVICE directory table (next paragraph) db db db dd dw db dd dw “32OS” 2 “$DDC” ? ? “$ERB” ? ? ; sig ; number of entries in table ; DDC POST buffer sig ; 32-bit pointer ; byte size ; ESCD sig ; 32-bit pointer ; bytes size The service identifier for client management functions is “$CLM.
Technical Reference Guide 8.5.1 SYSTEM ID AND ROM TYPE Applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register.
Chapter 8 System BIOS 8.5.3 TEMPERATURE STATUS The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system’s interior temperature. This function allows an application to check whether the temperature situation is at a Normal, Caution, or Critical condition. 8.5.4 DRIVE FAULT PREDICTION The Compaq BIOS directly supports Drive Fault Prediction for IDE-type hard drives. This feature is provided through two Client Management BIOS calls.
Technical Reference Guide System Timer In POST, the BIOS enables a timer in the south bridge component that generates an SMI once per minute. When the BIOS detects the SMI it checks status bits in the south bridge for device activity. If any of the device activity status bits are set at the time of the 1-minute SMI, BIOS resets the time-out minute countdown. The system timer can be configured through the Setup utility for counting down 0, 5, 10, 15, 20, 30, 40, 50, 60, 120, 180, or 240 minutes.
Chapter 8 System BIOS 8.6.1.3 Suspend Suspend is not supported in the Independent PM mode. 8.6.1.4 System OFF When the system is turned Off but still plugged into a live AC outlet the NIC, ICH2, and I/O components continue to receive auxiliary power in order to power-up as the result of a Magic Packet™ being received over a network. Some NICs are able to wake up a system from Standby in PM, most require their Windows/NT driver to reset them after one wake-up. 8.6.1.
Technical Reference Guide Appendix A ERROR MESSAGES AND CODES A. Appendix A ERROR MESSAGES AND CODES A.1 INTRODUCTION This appendix lists the error codes and a brief description of the probable cause of the error. NOTE: Errors listed in this appendix are applicable only for systems running hp/Compaq BIOS. NOTE: Not all errors listed in this appendix may be applicable to a particular system model and/or configuration. A.
Appendix A Error Messages and Codes A.3 POWER-ON SELF TEST (POST) MESSAGES Table A–2. Power-On Self Test (POST) Messages Table A-2.
Technical Reference Guide A.4 SYSTEM ERROR MESSAGES (1xx-xx) Table A–3. System Error Messages Table A-3. System Error Messages Message 101 102 103 104-01 104-02 104-03 105-01 105-02 105-03 105-04 105-05 105-06 105-07 105-08 105-09 105-10 105-11 105-12 105-13 105-14 106-01 107-01 108-02 108-03 109-01 109-02 109-03 Probable Cause Option ROM error System board failure (see note) System board failure Master int. cntlr. test fialed Slave int. cntlr. test failed Int. cntlr.
Appendix A Error Messages and Codes A.5 MEMORY ERROR MESSAGES (2xx-xx) Table A–4. Memory Error Messages Table A-4. Memory Error Messages Message 200-04 200-05 200-06 200-07 200-08 201-01 202-01 202-02 202-03 203-01 203-02 203-03 204-01 204-02 204-03 204-04 204-05 205-01 205-02 205-03 206-xx 207-xx 210-01 210-02 210-03 211-01 211-02 211-03 213-xx 214-xx 215-xx A.
Technical Reference Guide A.7 PRINTER ERROR MESSAGES (4xx-xx) Table A–6. Printer Error Messages Table A-6. Printer Error Messages A.8 Message 401-01 402-01 402-02 402-03 402-04 Probable Cause Printer failed or not connected Printer data register failed Printer control register failed Data and control registers failed Loopback test failed Message 402-11 402-12 402-13 402-14 402-15 402-05 402-06 402-07 402-08 402-09 402-10 Loopback test and data reg. failed Loopback test and cntrl. reg.
Appendix A Error Messages and Codes A.9 DISKETTE DRIVE ERROR MESSAGES (6xx-xx) Table A–8. Diskette Drive Error Messages Table A-8.
Technical Reference Guide A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx) Table A–10. Serial Interface Error Messages Table A-10.
Appendix A Error Messages and Codes A.12 SYSTEM STATUS ERROR MESSAGES (16xx-xx) Table A–11. System Status Error Messages Table A-11. System Status Error Messages Message 1601-xx 1611-xx Probable Cause Temperature violation Fan failure A.13 HARD DRIVE ERROR MESSAGES (17xx-xx) Table A–12. Hard Drive Error Messages Table A-12. Hard Drive Error Messages Message Probable Cause Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-51 Failed I/O read test 17xx-02 Exceeded max.
Technical Reference Guide A.14 HARD DRIVE ERROR MESSAGES (19xx-xx) Table A–13. Hard Drive Error Messages Table A-13.
Appendix A Error Messages and Codes A.16 AUDIO ERROR MESSAGES (3206-xx) Table A–15. Audio Error Messages Table A-15. Audio Error Message Message 3206-xx Probable Cause Audio subsystem internal error A.17 DVD/CD-ROM ERROR MESSAGES (33xx-xx) Table A–16. DVD/CD-ROM Drive Error Messages Table A-16. DVD/CD-ROM Drive Error Messages Message Probable Cause 3301-xx Drive test failed 3305-xx Seek test failed See Table A-18 for additional messages. A.18 NETWORK INTERFACE ERROR MESSAGES (60xx-xx) Table A–17.
Technical Reference Guide A.19 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx) Table A–18. SCSI Interface Error Messages Table A-18.
Appendix A Error Messages and Codes This page is intentionally blank.
Technical Reference Guide Appendix B ASCII CHARACTER SET B. Appendix B ASCII CHARACTER SET B.1 INTRODUCTION This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol.
Appendix B ASCII Character Set Table B-1.
Technical Reference Guide Appendix C KEYBOARD C. Appendix C KEYBOARD C.1 INTRODUCTION This appendix describes the HP/Compaq keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions. This appendix covers the following keyboard types: ♦ Standard enhanced keyboard.
Appendix C Keyboard C.2 KEYSTROKE PROCESSING A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power (+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated.
Technical Reference Guide C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer.
Appendix C Keyboard C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide). Packets received at the system’s USB I/F and decoded as originating from the keyboard result in an SMI being generated.
Technical Reference Guide C.2.3 KEYBOARD LAYOUTS Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems. Actual styling details including location of the Compaq logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary. C.2.3.
Appendix C Keyboard C.2.3.2 Windows Enhanced Keyboards 1 18 17 2 3 4 5 19 20 21 22 41 40 39 59 75 92 61 60 93 110 47 46 27 68 83 82 10 11 28 29 50 48 49 67 66 81 80 9 26 25 65 64 79 78 24 45 44 8 7 23 63 62 77 76 43 42 6 94 95 13 31 30 51 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 70 69 84 12 87 86 85 96 111 112 97 98 99 100 38 58 91 101 Figure C–5. U.S.
Technical Reference Guide C.2.3.3 Easy Access Keyboards The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. Depending on system, either a 7-button or an 8-button layout may be supplied. The 7-button Easy Access Keyboard uses the layout shown in Figure C-7 and is available with either a legacy PS/2-type connection or a Universal Serial Bus (USB) type connection.
Appendix C Keyboard C.2.4 KEYS All keys generate a Make code (when pressed) and a Break code (when released) with the exception of the Pause key (pos. 16), which produces a Make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
Technical Reference Guide C.2.4.2 Multi-Keystroke Functions Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions 55-57, 72, 74, 88-90, 100, and 101.
Appendix C Keyboard C.2.4.4 Easy Access Keystrokes The Easy Access keyboards (Figures C-7 and C-8) include additional keys (also referred to as buttons) used to streamline internet access and navigation.
Technical Reference Guide C.2.5 KEYBOARD COMMANDS Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic). Table C–1. Keyboard-to-System Commands Table C-1. Keyboard-to-System Commands Command Key Detection Error/Over/run BAT Completion BAT Failure Echo Acknowledge (ACK) Resend Keyboard ID Value 00h [1] FFh [2] AAh FCh EEh FAh FEh 83ABh Description Indicates to the system that a switch closure couldn’t be identified.
Appendix C Keyboard Table C–2. Keyboard Scan Codes Table C-2. Keyboard Scan Codes Key Pos.
Technical Reference Guide Table C-2.
Appendix C Keyboard Table C-2. Keyboard Scan Codes (Continued) Key Pos. 81 82 83 84 85 86 87 Legend N M , . / Shift (right) 88 89 90 91 1 2 3 Enter 92 93 94 95 96 97 Ctrl (left) Alt (left) (Space) Alt (right) Ctrl (right) 98 99 100 101 102 103 104 110 0 .
Technical Reference Guide Table C-2. Keyboard Scan Codes (Continued) Key Pos.
Appendix C Keyboard C.3 CONNECTORS Two types of keyboard interfaces are used in HP/Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to Chapter 5 “Input/Output” of this guide.
Technical Reference Guide Appendix D COMPAQ/INTEL NETWORK INTERFACE CONTROLLER ADAPTERS D. Appendix D Compaq/Intel Network Interface Controller Adapters D.1 INTRODUCTION This appendix describes Compaq/Intel Network Interface Controller adapters that may be included in the standard configuration on some models and available as options for all models.
Appendix D Compaq/Intel Network Interface Controller Adapters D.2 FUNCTIONAL DESCRIPTION The Intel PRO/100+ and the PRO/100 S Management Adapters are based on the Intel 82559 and 82550 Ethernet Controllers (respectively) supported by firmware in flash ROM (see figure below). Each adapter can operate in half- or full-duplex modes and provides auto-negotiation of both mode and speed.
Technical Reference Guide D.2.1 AOL FUNCTION The adapter’s Alert-On-LAN (AOL) function provides a AOL-compliant system unit with the ability to communicate system status to a management console, even while the system is powered down. When installed in an AOL-compliant system, the adapter receives alert messages from the system’s south bridge over the PCI bus. Each alert message decoded by the adapter results in a pre-constructed status message being transmitted over the network to a management console.
Appendix D Compaq/Intel Network Interface Controller Adapters D.2.3 IPSEC FUNCTION The 82550 controller used on the Intel PRO/100 S Management Adapter includes an encryption engine that provides on-the-fly encryption and/or authentication of transmit data without additional use of system memory and software. This function, referred to as IP security (IPSEC), uses a configurable algorithm and established Data Encryption Standards (DES) to provide high performance (full transmission rate) encryption.
Technical Reference Guide D.3 POWER MANAGEMENT SUPPORT These adapters support APM and ACPI power management environments as well as the Wiredfor-Management (WfM) and Wake-On-LAN (WOL) standards. The adapter is designed to be powered up as long as the system unit is plugged into a live AC outlet to provide system “wakeup” functionality. Power is provided by either the auxiliary 3.3 VDC power rail of the PCI bus (when installed in systems compliant with PCI ver. 2.
Appendix D Compaq/Intel Network Interface Controller Adapters D.4 ADAPTER PROGRAMMING Programming the adapter consists of configuration, which occurs during POST, and control, which occurs at runtime. D.4.1 CONFIGURATION The adapter’s 82559 or 82550 NIC controller is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4 of this guide. The PCI configuration registers are listed in the following table: Table D-1.
Technical Reference Guide D.5 NETWORK CONNECTOR The figure below shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly. Activity LED Speed LED Pin 1 2 3 6 Description Transmit+ TransmitReceive+ Receive- 8 7 6 5 4 3 2 1 Figure D-3. D.6 Ethernet TPE Connector (RJ-45, viewed from card edge) ADAPTER SPECIFICATIONS Table D-3. Adapter Operating Specifications Table D-3.
Appendix D Compaq/Intel Network Interface Controller Adapters This page is intentionally blank.
INDEX I.
keyboards, Easy Access, C-7 keys, Easy Access, C-10 keys, Windows, C-9 LED, 5-32 LED indications, 4-26 LED, HD, 4-32 LED, Power, 4-32 low voltages, 7-8 LPC bus, 4-7 LPC47B34x I/O controller, 4-31 Magic Packet, 5-34 mass storage, 2-12 memory detection, 8-4 memory map, 3-7 microphone, 5-26 mouse interface, 5-18 network interface controller, 2-13, 5-32 network interface controller card, D-1 network support, 5-32 NIC, 5-32 NIC card, D-1 notational conventions, 1-2, 1-3, 1-4 option ROM, 4-7 options, 2-3 parallel
