Intel Optane DC Persistent Memory - Configuration and Setup White Paper

23TECHNICAL WHITE PAPER
RESOURCE LINKS
1. Intel
®
Optane™ DC Persistent Memory Module References
https://www.intel.com/content/www/us/en/architecture-and-technology/optane-dc-
persistent-memory.html
2. Conguring and Using NVDIMM
Intro to Overall Architecture http://pmem.io/2014/08/27/crawl-walk-run.html
3. Conguration Tools
Ipmctl Documentation and Source: https://github.com/intel/ipmctl
NDCTL: https://pmem.io/ndctl
4. Developing Applications and SW for Persistent Memory
Intel
®
Developer Zone
SNIA – Persistent Memory and the SNIA NVM Programming Model
Persistent Memory Development Kit (PMDK) and PMDK Programmers Guide are available on
https://pmem.io/
Glossary
• DCPMM: Data Center Persistent Memory Module.
• DRAM Memory/DIMM: Dynamic Random-Access Memory - Standard memory module.
• NVDIMM: Non-Volatile memory.
• DIMM: Dual In-Line Memory Module.
• Namespace: Similar to an NVMe
®
Namespace or a Logical Unit (LUN) on a SCSI disk, this is a software
mechanism for managing ranges of persistence on DCPMMs.
• Region: A region is a grouping of one or more NVDIMMs, or an interleaved set, that can be divided up into one or
more Namespaces.
• DAX: Direct Access - File system extensions to bypass the page cache and block layer to memory map persistent
memory, from a PMEM block device, directly into a process address space.
• Interleaved Memory – A technique for spreading address across multiple memory devices to increase the bandwidth.
• NUMA Memory Mode – Non-Uniform Memory Access – shared memory architecture that describes the
placement of main memory modules with respect to processors in a multiprocessor system.
• BTT: Block Translation Table
°
BTT is utilized to provide atomic sector updates. When DCPMM is used in Storage Mode, the operating
system and storage subsystem expect to be writing to a standard block size, which is 4 kilobytes. BTT
emulates a standard block size and ensures that writes are committed in 4K chunks. This ensures that all data
that is expected to be written will be committed to media.
• IMC: Integrated Memory Controller.
°
On the Intel
®
Xeon
®
SP processors, there are two memory controllers per processor. Each memory controller
contains 3 channels. A single IMC is represented by the group of 3 (Z6) or 6 (Z8) DIMM sockets on one side of
the processor.
• Zero Copy: Computer operations in which the CPU does not perform the task of copying data from one memory
area to another. This is frequently used to save CPU cycles and memory bandwidth.
1
Intel® Optane™ DC Persistent Memory can be used as main memory on select HP Z6 G4 and Z8 G4 workstations with Intel
®
Xeon
®
8200, 6200, 5200
and select 4200 series processors, Windows 10 64bit for Workstations version 1903 or higher and select Linux releases. Latency dierences between
DCPMM and DRAM are inherent. For data that is not in DRAM cache, DCPMM could experience latencies that are 10x versus data directly from DRAM.
2
Intel® Optane™ DC Persistent Memory can be used as main memory. Latency dierences between DCPMM and DRAM are inherent. For reads that
are not in DRAM cache, accesses from DCPMM could experience latencies that are 10x versus reads directly from DRAM.
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CONTENTS & NAVIGATION
1
Introduction
5
DCPMM Security
Overview
System Requirements
6
System Setup Overview
8
Appendices