HP Vectra 500 Series PC Models: 520 5/xx 525 5/xx Hardware and BIOS Technical Reference Manual September 1996
Notice The information contained in this document is subject to change without notice. Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance, or use of this material.
Preface This manual is a technical reference and BIOS document for engineers and technicians providing system level support for HP Vectra 500 Series PCs for models 520 5/xx and 525 5/xx. It is assumed that the reader possesses a detailed understanding of ATcompatible microprocessor functions and digital addressing techniques. Technical information that is readily available from other sources, such as manufacturers’ proprietary publications, has not been reproduced.
Conventions The following conventions are used throughout this manual to identify specific elements: ❒ Hexadecimal numbers are identified by a lower case h. For example, 0FFFFFFFh or 32F5h ❒ Binary numbers and bit patterns are identified by a lower case b. For example, 1101b or 10011011b Bibliography ❒ System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7) by Phoenix Technologies. Addison-Wesley (publisher).
Contents 1 HP Vectra 500 Series Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 D4051-63001 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 D4051-63001- Desktop Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 D4051-63001 - Minitower Models . . . . . . . . . . . . . . . . . . .
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 System Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 System Board Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SiS Chipset . . . . . . . . . . . . . .
Devices on the Processor Local Bus (D4051-63001). . . . . . . . . . . . . 44 Main Memory (UMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Cache Memory (D4051-63001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Level-1 Cache Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Level-2 Cache Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 System Board (P/Ns D3657-63001 and D3661-63001) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 D3657-63001 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Desktop Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Minitower Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 D3661-63001 Models. . . . . . . .
Superscalar Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Dynamic Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Instruction and Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Summary of the HP/Phoenix BIOS Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 HP/Phoenix BIOS Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Updating the System ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Error Diagnostics and Suggested Corrective Actions . . . . . . . . . . . . . . . 83 Little Ben . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security Menu (BIOS version: GJ.07.xx) . . . . . . . . . . . . . . . . . . . . . . . .102 Power Menu (BIOS version: GJ.07.xx) . . . . . . . . . . . . . . . . . . . . . . . . . .102 Summary Configuration Screen (BIOS version: GJ.07.xx) . . . . . . . . . .103 I/O Addresses Used by the System (BIOS version: GJ.07.xx) . . . . . . . . 104 System Memory Map (BIOS version: GJ.07.xx) . . . . . . . . . . . . . . . . . . . 104 BIOS I/O Port Map (BIOS version: GJ.07.xx) . . . . . . . . . . . . . . . . . . . . .
Matrox MGA Millennium Video Controller Card . . . . . . . . . . . . . . 127 MGA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MGA Video Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Available MGA Video Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Further Information About MGA . . . . . . .
1 HP Vectra 500 Series This chapter provides a description of the HP Vectra 500 Series desktop (Models 520 5/xx) and minitower (Models 525 5/xx) computers with detailed system specifications. The HP Vectra 500 Series computers are Pentium processor-based, constructed around the Peripheral Component Interconnect (PCI) bus and Industry Standard Architecture (ISA) bus.
1 HP Vectra 500 Series Introduction Introduction Three group types have been defined to help identify the various system configurations available on the HP 500 Series desktop and minitower packages. Within each group, a product number and the appropriate HP Vectra 500 Series model have been associated with the HP Service Part Number. The HP Service Part Numbers are: • D4051-63001 • D3657-63001 • D3661-63001 An HP Service Part Number group contains details of a specific system configuration.
1 HP Vectra 500 Series System Overview System Overview D4051-63001 Models The HP Service Part Number D4051-63001 group contains HP Vectra 500 Series models that have the following features: Unified Memory Architecture (UMA), main memory upgradable to 192 MB, and the SiS (Silicon Integrated System) 6205 video graphic controller. D4051-63001- Desktop Models The following table shows the models and their associated product numbers.
1 HP Vectra 500 Series System Overview D3657-63001 Models The HP Service Part Number D3657-63001 group contains HP Vectra 500 Series models that have the following features: separate main memory and video memory, and an integrated 32/64 Ultra VGA video graphic controller. D3657-63001 - Desktop Models The following table shows the models and their associated product numbers.
1 HP Vectra 500 Series System Overview D3661-63001 Model The HP Service Part Number D3661-63001 group contains one HP Vectra 500 Series model that has the following features: separate main memory and a Matrox MGA millennium video card. D3661-63001 - Minitower Model The following table shows the model and its associated product number.
1 HP Vectra 500 Series System Overview Features Level-two cache memory (optional) HP Service Part Number: D4051-63001 HP Service Part Number: D3657-63001 and D3661-63001 256 KB synchronous cache are standard on the following models: U.S.
1 HP Vectra 500 Series System Overview Comparison of HP Vectra 500 Series Desktop and Minitower Models The HP Vectra 500 Series PCs come in two packages, a desktop box and a minitower box. The following table shows the differences between the two packages.
1 HP Vectra 500 Series System Overview Principal Features This section includes the principal features of the system board that are available on both the desktop and minitower packages: • An Enhanced IDE controller with two channels on the PCI bus. • Rear panel connectors: ❒ 1 mouse socket ❒ 1 keyboard socket ❒ 1 display connector ❒ 1 parallel connector ❒ 2 serial ports • a system ROM (using flash ROM technology) that can be easily updated with the latest firmware, using the Phlash.
1 HP Vectra 500 Series System Overview Physical and Environmental Specifications The following tables show the physical and environmental specifications of the minitower and desktop computers. All the characteristics valid for both computers are grouped together at the end of the table. Computer Type Minitower Characteristic Weight Description 13 kilograms (28.7 pounds) (excluding keyboard and display) Dimensions 44 cm (Depth) by 19.2 cm (Width) by 43.8 cm (Height) (17.3 inches by 7.6 inches by 17.
1 HP Vectra 500 Series System Overview Computer Type Characteristic These characteristics are valid for both the minitower and desktop computers.
1 HP Vectra 500 Series System Overview Power Consumption NOTE The figures given below are valid for both the minitower and desktop computers with a standard configuration—no expansion cards and no CD-ROM drive. For other configurations, the power consumption values will be higher. 1. NOTE Full Power Mode <44 W Standby Mode <29 W Suspend Mode <24 W Off < 5 W1 The power supply in the computer continues to supply power to the CMOS memory, even when turned off.
1 HP Vectra 500 Series System Overview Rear Panel Connectors The external connectors on the rear panel of the computer are used to connect the mouse, keyboard and display. The 25-pin parallel port can be used for connecting a parallel printer, while the two 9-pin buffered serial ports are for serial printers. The following diagram shows the rear panel connectors for the minitower and desktop computers.
1 HP Vectra 500 Series CD-ROM Drive Specifications CD-ROM Drive Specifications WARNING To avoid electrical shock and harm to your eyes by laser light, do not open the CD-ROM drive enclosure. Do not attempt to make any adjustment to the CDROM drive. Refer servicing to qualified personnel only. The CD-ROM drive is a Class 1 laser product. Data Capacity •656 MB (Mode 1) •748 MB (Mode 2) Data Transfer Rate Depends on the model. The single-speed rate is 150 KB/sec.
1 HP Vectra 500 Series CD-ROM Drive Specifications 26
2 System Board - (SiS Chipset) (Part Number: D4051-63001) This section describes the components and features of the SiS (Silicon Integrated System) chipset-based system board. This system board has the HP Service Part Number: D4051-63001.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Overview Overview The type of system board described in this section uses shared memory based on UMA (Unified Memory Architecture), meaning that there is no dedicated frame buffer used by the video controller (SiS 6205). Instead, the controller uses a portion of the system memory as a frame buffer. The following tables show the models that are associated with the HP Service Part Number: D4051-63001.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Overview Configuration • Supported Processor: P54CS. • Level-2 (L2) 256 KB cache sockets. • UMA Chipset from SiS consisting of three chips that interface between the three main buses (the Host bus, the PCI bus and the ISA bus): SiS 5511: Host/PCI bridge, L2 cache memory controller and memory controller. SiS 5512: PCI Local Data Buffer (Data Path). SiS 5513: PCI/ISA bridge, plus integrated functions.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) System Board Architecture System Board Architecture The following diagram shows the architecture of the various components and the SiS chipset on the system board.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) System Board Physical Layout System Board Physical Layout The following system board diagram will help you identify where the different components and connections are located on the board. Refer to the section System Board Switches and Jumpers (D4051-63001) on page 38 for switches and jumper settings.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset SiS Chipset The SiS chipset consists of three chips, each encapsulated in a 208-pin plastic quad flat pack (PQFP) package, that interface between the three main buses (the Host bus, the PCI bus and the ISA bus): • The PCMC chip (SiS 5511) is a combined PL/PCI bridge and cache controller and main memory controller and PCI arbiter. • The PLDB chip (SiS 5512) provides the PCI local data buffer/path.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Pentium Processor Processor Local Bus (64 bit, 60/66 MHz) Level-2 Cache Host Bridge & Memory Controller SiS 5511 CPU PCI Interface Interface Cache Control SiS 5512 Control Memory Control UMA Arbitration Main Memory Control Data Path SiS 5512 Video Controller SiS 6205 PCI Bus (32 bit, 30/33 MHz) PCI/ISA Bridge SiS 5513 PCI Bus ISA Bus Interface Interface IDE Controller DMA Controller Interrupt Controller BIOS (Flash Memory 28
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Host/PCI Bridge (SiS 5511 Chip) The SiS 5511 chip (PCMC) bridges between the host bus and the PCI local bus. This device integrates cache and memory control functions and provides bus control functions for the transfer of information between the micro-processor, cache, main memory and the PCI bus. The PCMC monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Feature Summary Function Features Cache controller ❒ ❒ ❒ ❒ ❒ Integrated DRAM controller ❒ Supports four banks of SIMMs. ❒ Supports 256K, 512K, 1MB, 2MB, 4MB, 16MB 70ns FP/EDO DRAM. ❒ Supports 4K refresh DRAM. ❒ Supports 3V or 5V DRAM. ❒ Supports symmetrical and asymmetrical DRAM. ❒ Supports 32 bits/64 bits mixed mode configuration. ❒ Supports concurrent write back. ❒ Supports Read Cycle Power Saving Mode.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Data Path (SiS 5512 Chip) The SiS 5512 PCI Local Data buffer (PLDB) provides bidirectional data buffering among the 64-bit Host Data Bus, the 64/32-bit Memory Data Bus, and the 32-bit PCI Address/Data Bus. The PLDB incorporates three FIFOs (First In First Out) and one read buffer among the bridges of the CPU, PCI, and memory buses.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Play port. The PSIO supports two bus master IDE channels providing up to four IDE devices. The PSIO does not require any IDE buffering to be used, and therefore no IDE buffers are used. The SiS 5513 chip consists of: • • • • • • • A PCI bridge that translates PCI cycles onto the ISA bus. ISA master/DMA device that translates cycles onto the PCI bus. A seven-channel programmable DMA controller.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset System Board Switches and Jumpers (D4051-63001) The system board switches and jumpers are used to configure certain aspects of the computer. SW1 Switch This switch is multi-purpose and is used to modify Flash, CMOS and password settings. Switch Default Setting 1 OFF Flashing Enable Flashing Disable Updating the BIOS. Set the security mode. Set the switch to the ON position to prevent the BIOS from being upgraded.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset SW2 Switch This switch is used to select the internal CPU frequency by defining the CPU Bus Frequency / CPU Frequency ratio. If the processor is upgraded, the ratio might have to be changed to adapt to the new processor.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Cache Jumper This jumper (J6) selects either synchronous or asynchronous cache type. If the PC is not installed with any level-2 cache, the default jumper setting is synchronous cache. The following illustration shows the two cache-type jumper settings.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) SiS Chipset Processor Socket (D4051-63001) The microprocessor is packaged in a pin-grid-array (PGA), which is seated on the system board in a zero-insertion-force (ZIF) socket. Memory Sockets (D4051-63001) There are six main memory module sockets available with the HP Vectra 500 Series minitower and desktop computers. The sockets are arranged in three banks (A to C), allowing memory installation up to a maximum of 192 MB.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Backplane (D4051-63001) Backplane (D4051-63001) Desktop Backplane The HP Vectra 500 Series desktop backplane supports two 16-bit ISA (Industry Standard Architecture) cards, one 32-bit PCI (Peripheral Component Interconnect) card and has one combination slot for an ISA or PCI card.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Backplane (D4051-63001) Minitower Backplane The HP Vectra 500 Series minitower backplane supports three 16-bit ISA (Industry Standard Architecture) cards, two 32-bit PCI (Peripheral Component Interconnect) cards and has one combination slot for an ISA or PCI card.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the Processor Local Bus (D4051-63001) Devices on the Processor Local Bus (D4051-63001) Main Memory (UMA) The SiS 5511 chip can support single-sided or double-sided 64/72 bits (with or without parity) FP (Fast Page mode) or EDO (Extended Data Output) DRAM (dynamic random-access memory) modules. Half populated banks are also supported. The PC can use 60 ns EDO or 70 ns FP DRAM.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the Processor Local Bus (D4051-63001) Level-1 Cache Memory The L1 cache memory is divided into two separate banks: • L1 I-cache for instruction words. • L1 D-cache for data words. For more information about Level-1 cache, refer to “Instruction and Data Cache” on page 46. Level-2 Cache Memory The L2 cache memory, when installed, has a 32-byte line size. It is controlled by the Host Bridge chip (SiS 5511) in the system board chipset.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the Processor Local Bus (D4051-63001) Superscalar Architecture The Pentium processor’s superscalar architecture has two instruction pipelines and a floating-point unit, each capable of independent operation. The two pipelines allow the Pentium to execute two integer instructions in parallel, in a single clock cycle.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the Processor Local Bus (D4051-63001) The data cache tags (directory entries used to reference cached memory pages) are triple-ported to support two data transfers and an inquire cycle in the same clock cycle. The code cache tags are also triple-ported to support snooping (a way of tracking accesses to main memory by other devices) and split line accesses.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the PCI Bus Devices on the PCI Bus Graphics/Integrated Video (D4051-63001) The HP Vectra 500 Series PC uses the SiS 6205 video controller and supports video resolutions up to 1280 x 1024. Video Controller As explained earlier, the SiS 6205 video controller supports the UMA architecture, and therefore no dedicated video memory is loaded on the system board.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the PCI Bus Integrated Drive Electronics (IDE) Controller The IDE controller is implemented as part of the PCI/ISA bridge chip. It is driven from the PCI bus and has PCI-Master capability. It supports Enhanced IDE (EIDE) and Standard IDE (Bus Master IDE). To use the Enhanced IDE features, though, hard disk drives must be compliant with Enhanced IDE.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the PCI Bus Minitower Configuration Connections to Data Cables One hard disk drive 1. Bootable hard disk drive: Master connector, HDD data cable Two hard disk drives 1. Bootable hard disk drive: 2. Second hard disk drive: Master connector, HDD data cable Slave connector, HDD data cable Three hard disk drives 1. Bootable hard disk drive: 2. Second hard disk drive: 3.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the PCI Bus The three DMA modes allow the following transfer rates: Mode 0 1 2 Cycle time (ns) 480 150 120 Transfer rate (MBytes/s) 4.2 13.3 16.7 Operated in slave mode, the IDE controller saturates the PCI bus with transfers, thus limiting the actual achieved transfer rate to less than 10 MBytes per second. Operated in master mode, though, the IDE controller is allowed to work autonomously of the processor, and the full 16.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the ISA Bus Devices on the ISA Bus Super I/O Chip (NS 87308 or NS 87307) The basic input/output control functions are provided by the Super I/O chip, the NS 87308 or NS 87307. The Super I/O chip is contained within a 160-pin PQFP package.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the ISA Bus Feature Summary Function Features Floppy disk controller ❒ Software compatible with the DP8473, the 765A, and the N82077 ❒ 16-byte FIFO (default disabled) ❒ Burst and non-burst modes ❒ Perpendicular recording drive support ❒ New high-performance internal digital data separator (no external filter components required) ❒ Low-power CMOS with enhanced power-down mode ❒ Automatic media-sense support UARTs ❒ Software compatible
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the ISA Bus Function Features 16 Single-Bit General Purpose I/O ports (GPIO) ❒ Modifiable addresses that are referenced by a 16-bit programmable register. ❒ Programmable direction for each signal (input or output). ❒ Programmable drive type for each output pin (open-drain or push-pull). ❒ Programmable option for internal pull-up resistor on each input pin. ❒ A back-drive protection circuit. Clock source options ❒ Source is a 32.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) Devices on the ISA Bus Floppy Drive Controller The Floppy Drive Controller (FDC) is software and register compatible with the 82077AA, and 100% IBM compatible. It has an A and B drive-swapping capability and a non-burst DMA option. The FDC supports any combination of the following: tape drives, 3.5 inch flexible disk drives, 5.25 inch flexible disk drives.
2 System Board - (SiS Chipset) (Part Number: D4051-63001) BIOS (version: GX.07.xx) BIOS (version: GX.07.xx) The following section is an overview of the BIOS features available with the system identified by the BIOS version: GX.07.xx, installed on the HP Vectra 500 Series PC models with an HP Service Part Number: D4051-63001. For further detailed information about the BIOS, refer to chapter 4, Summary of the HP/Phoenix BIOS.
3 System Board (P/Ns D3657-63001 and D3661-63001) The two system boards described in this chapter use the Intel SB82437/8 PCI chipset. The two boards are the same except that D3657-63001 has an integrated (onboard) video controller and memory, whereas D3661-63001 uses a Matrox Millennium video card for its video controller and memory.
3 System Board (P/Ns D3657-63001 and D3661-63001) Overview Overview This section lists the 520 and 525 models and product numbers that use the two system boards D3657-63001 and D3661-63001. D3657-63001 Models Desktop Models The following table lists the desktop models and products that use the D3657-63001 system board.
3 System Board (P/Ns D3657-63001 and D3661-63001) Overview D3661-63001 Models Minitower Models The following table lists the minitower models and products that use the D3661-63001 system board. Model 525 MCx2 5/200 Product Number D4471A 1 =Includes CD-ROM 2 =Includes CD-ROM and Modem/Audio Configuration Summary • Supported processors: P54C and P54CS. • Level-2 cache memory socket - supports 256-KB cache memory module (the module is already installed in some PCs).
3 System Board (P/Ns D3657-63001 and D3661-63001) System Board Architecture System Board Architecture The following diagram shows the functional relationship between the various components on the system board.
3 System Board (P/Ns D3657-63001 and D3661-63001) System Board Physical Layout System Board Physical Layout The following diagram shows the physical layout of the system board. * * This video upgrade applies only to the models with integrated video controller.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features Principal Components and Features PCI Chipset The PCI chipset consists of four chips that interface between the three main buses (the processor’s local (PL) bus, the PCI bus, and the ISA bus): • The PL/PCI bridge chip (SB82437FX-66) which also provides control for the PCI bus, level-2 cache memory, and main memory.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features PCI, Cache and Memory Controller (SB82437FX-66) The SB82437FX-66 device integrates cache and memory control functions and provides bus control functions for the transfer of information between the microprocessor, cache, main memory and the PCI bus. The cache controller supports the Pentium Cache Write-Back mode and 256 KB of direct mapped, write-back level-two cache, using synchronous pipeline burst SRAMs.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features Function Features PCI master interface ❒ Provides for programmable PCI bus memory regions in memory address map ❒ Supports PCI bus burst cycles for 64-bit and 32-bit misaligned Pentium reads and writes ❒ Optional posting of PCI memory and I/O writes ❒ Optional buffering of PCI memory writes ❒ Optional read-ahead for processor to PCI accesses PCI bus arbiter ❒ Supports PCI bus arbitration for up to four masters ❒ Suppor
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features The PCI/ISA Bridge and IDE Controller (SB82371FB) The SB82371FB device serves as a bridge between the PCI bus and the ISA expansion bus, and incorporates a two-channel PCI IDE controller. It incorporates the logic for a PCI interface, a DMA interface, a DMA controller that supports fast DMA transfers, data buffers to isolate the PCI and ISA buses, Timer/Counter logic, and NMI control logic.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features Function Features ISA bus controller (for SB82371FB only) ❒ Fully compatible with ISA bus standard ❒ Supports asynchronous ISA bus operation up to 16 MHz ❒ Integrates: ❒ two 82C37A DMA controllers ❒ two 82C59A interrupt controllers ❒ 82C54 timer ❒ hidden ISA refresh controller ❒ support for BIOS ❒ port A, B and NMI logic Fast IDE controller (for SB82371FB only) ❒ ❒ ❒ ❒ Supports PIO and Bus Master IDE Supports up to Mo
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features Switch Setting 1-4 - Switch Functions Default Setting Selects system board speed settings, refer to “Bus Frequencies” on page 72. Open Enables User and Administrator passwords. Closed Clears User and Administrator passwords. Open CMOS memory acts as a non-volatile store for the Setup program.. Closed Clears the Setup configuration data in the CMOS memory.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features Advanced Power Management (APM) The Advanced Power Management (APM) is a standard, defined by Intel and Microsoft, for a power-saving mode that is applicable under a wide range of operating systems. The version APM 1.1 supports the following modes: Fully-on, Standby, Suspend, and Off. The Suspend mode, which also used to be known as Sleep, is now managed at the operating system level only.
3 System Board (P/Ns D3657-63001 and D3661-63001) Principal Components and Features HP Vectra 500 Series Minitower Backplane The HP Vectra 500 Series minitower backplane supports three 16-bit ISA (Industry Standard Architecture) cards, two 32-bit PCI (Peripheral Component Interconnect) cards and has one combination slot for an ISA or PCI card.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the Processor Local Bus Devices on the Processor Local Bus The following subsystems are associated with the Processor Local bus: • Intel Pentium microprocessor • cache memory • main memory Pentium Processor The Pentium processor uses a 64-bit bus, and is 100% compatible with Intel’s family of x86 processors. All application software that has been written for Intel 80386 and Intel 80486 processors can run on the Pentium without modification.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the Processor Local Bus Using the pipelines halves the instruction execution time and almost doubles the performance of the processor, compared with an Intel486 microprocessor of the same frequency. Floating Point Unit (FPU) The Floating Point Unit incorporates optimized algorithms and dedicated hardware for multiply, divide, and add functions. This increases the processing speed of common operations by a factor of three.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the Processor Local Bus Individual pages of memory can be configured as cacheable or noncacheable by software or hardware. They can also be enabled and disabled by hardware or software. Data Integrity The processor uses a number of techniques to maintain data integrity.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the Processor Local Bus Switch Switch 1 2 ProcessorLocal Bus Frequency Open Closed 66 MHz Closed Open Open Closed 4 7 Frequency Ratio (Processor: Local Bus) Closed Closed Closed 2.5 166 MHz 60 MHz Open Closed Closed 3.0 180 MHz 66 MHz Open Closed Closed 3.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the Processor Local Bus Main Memory There are six main memory module sockets on the system board, enabling up to 128 MB of main memory to be installed. The sockets are arranged in three banks (A to C). Memory modules must be installed in pairs which are the same size to ensure that all the memory is configured correctly. Fast memory access, with the timing pattern 7-2-2-2, is achieved by installing EDO RAM.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the PCI Bus Devices on the PCI Bus The PL/PCI bridge is implemented within the Intel SB82437FX-66 chip (see page 63). It is responsible for transferring data between the Processor-Local bus and the PCI bus. As a PCI bus slave, this chip becomes the PL bus master, to generate DRAM requests on behalf of other PCI bus masters. It supports PCI bus burst cycles, posted writes to DRAM for PCI burst writes, and read-ahead from DRAM for PCI burst reads.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the PCI Bus S3 Trio 64PnP Video Controller The integrated video subsystem consists of a PCI bus video controller and a DRAM array. The PC uses the S3 Trio 64 PnP video controller. This video controller embeds a RAMDAC, and supports video resolutions of up to 1280 x 1024. The S3 Trio 64PnP video controller offers full compatibility with VGA.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the PCI Bus with two connectors. For desktop models, the primary channel cable is fitted with two connectors, and the secondary channel cable is fitted with one connector. With EIDE, it is possible to have a fast device, such as a hard disk drive, and a slow device, such as a CD-ROM drive, on the same channel without affecting the performance of the fast device.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the ISA Bus Devices on the ISA Bus ThePCI/ISA Bridge chip (also known as PIIX, or as the system I/O chip, SIOA) is an Intel SB82371FB. It is responsible for transferring data between the PCI bus and the ISA expansion bus. As the ISA bus controller, the chip supports asynchronous ISA bus operation up to 16 MHz.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the ISA Bus • Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible) • Enhanced mode (Enhanced Parallel Port or EPP compatible) • High speed mode (MS/HP Extended Capabilities Port or ECP compatible). It can be programmed as LPT1 (378h, IRQ7), LPT2 (278h, IRQ5), or disabled. Floppy Drive Controller (FDC) The integrated Floppy Drive Controller (FDC) supports 3.5-inch and 5.25inch floppy disk drives, and tape drives.
3 System Board (P/Ns D3657-63001 and D3661-63001) Devices on the ISA Bus System ROM The PC uses 128 KB of 200 ns, Flash EEPROM implemented within a single 256 K X 8-bit ROM chip. This is a ROM that can be returned to its unprogrammed state, by the application of appropriate electrical signals to its pins, and then reprogrammed with the latest upgrade firmware.
4 Summary of the HP/Phoenix BIOS This chapter gives an overview of the two different versions of the HP/Phoenix BIOS installed on the HP Vectra 500 Series PC models.
4 Summary of the HP/Phoenix BIOS Overview Overview The information concerning the different versions of the HP/Phoenix BIOS installed on the HP Vectra 500 Series models described in this chapter is divided into two main sections: • The system BIOS identified by the version number GX.07.xx, installed on the HP Vectra 500 Series PC models with an HP Service Part Number: D4051-63001. For a complete list of the computers associated with this part number, refer to “D4051-63001 Models” on page 15.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS Description Before flashing, it is necessary to disable the “Secure Mode” switch on the system switches, and to type in the System Administrator Password when starting up the computer. The PCI and PnP information is erased in the process. Do not switch off the computer until the system BIOS update procedure has completed, successfully or not, since irrecoverable damage to the ROM may otherwise be caused.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS Description Little Ben Little Ben is an HP application specific integrated circuit (ASIC) that is connected between the chipset and the processor. It has been designed to act as a companion to the Super I/O chip. It contains the following: • Hard and soft power control. • BIOS timer: hardware-wired, 50 ms long 80 Hz beep module; automatic blinker that feeds the LEDs module with a 1 Hz oscillator signal.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) HP/Phoenix BIOS (BIOS version: GX.07.xx) This section gives an overview of the HP/Phoenix BIOS identified by the BIOS version: GX.07.xx associated with the HP Vectra 500 Series models, HP Service Part Number D4051-63001. The information in this section includes the following: • Setup Program: with menu-driven context-sensitive help (in U.S. English only).
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) Some fields disappear completely when a choice in another field makes their appearance inappropriate (for example, the “Key auto-repeat speed” and “Delay before auto-repeat” fields disappear when the user selects Yes in the “Running Windows 95” field, since these parameters can then be set within the operating system). Configuration Menu (BIOS version: GX.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) Disabling a device in the Configuration Menu (for example, Serial port B in the diagram above) has the advantage of freeing the resources (such as IRQs and peripheral addresses). Disabling a device in the Security Menu disables the access, does not free the resources, but has the advantage of temporarily disabling the device without losing the configuration settings.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) be locked, so as to prevent the exporting of data. Writes to the hard disk drive boot sector can also be locked, for instance as a protection against viruses.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) The following summary screen is an example of a system configuration. HP Vectra VE5/100 Series 3 — Copyright 1995 Hewlett-Packard — QA.01.00 Any line of text can be entered here as a ‘tatoo’ for the PC BIOS Version : GX.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) I/O Addresses Used by the System (BIOS version: GX.07.xx) Peripheral devices, accessory devices and system controllers are accessed via the system I/O space. The 64 KB of addressable I/O space comprises 8-bit and 16-bit I/O ports (these are registers that are located in the various system components).
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) BIOS I/O Port Map (BIOS version: GX.07.xx) This section describes the HP BIOS port map. The next section provides more details about how the BIOS uses the system board components mentioned in the I/O port list.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) I/O Address Ports Function 0378-037F Parallel port 2 03B0-03BB Integrated video graphics controller 03BC--03BF Parallel port 1 03C0-03DF Integrated video graphics controller 03E8-03EF Serial port 3 03F0-03F5 Floppy disk controller 03F6 IDE controller primary channel 03F7 Floppy disk controller 03F8-03FF Serial port 1 0496-0497 Internal ports (or HP reserved) 0CF8-0CFF Used for PCI configuration1 1.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) The following table summarizes how the DMA channels are allocated. First DMA controller (used for 8-bit transfers) Channel 0 1 2 3 Function Available Available or ECP mode for parallel port Flexible disk I/O Available or ECP mode for parallel port Second DMA controller (used for 16-bit transfers) Channel 4 5-6 6-7 Function Cascade from first DMA controller Available Available Interrupt Controllers (BIOS version: GX.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) IRQ15(77h) IRQ3(0Bh) IRQ4(0Ch) IRQ5(0Dh) IRQ6(0Eh) IRQ7(0Fh) Free, if not used by secondary channel of IDE controller Free, if not used for serial port Free, if not used for serial port Free, if not used for parallel port Floppy disk drive controller Free, if not used for parallel port Using the Setup program: • • • • • IRQ3 can be made available by disabling serial ports 2 and 4.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) To see the tests performed during the POST, press when the initial HP “Vectra” logo appears, and the display will switch to text mode. In this mode, a summary configuration screen will be displayed at the end of the POST. Devices, such as memory and hard disks, are configured automatically. The user is not requested to confirm the change. However, the user is prompted if a device is found to have gone missing since the previous boot.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) Internal Cache Memory Test Initialize the Video Test External Cache Shadow SCSI ROM 8042 Self-Test Timer 0/Timer 2 Test DMA Subsystem Test Interrupt Controller Test Real-Time Clock Test RAM Address Line Independence Test Size Extended Memory Real-Mode Memory Test (First 640KB) Shadow RAM Test Protected Mode RAM Test (Extended RAM) Keyboard Test 96 Tests the processor’s internal level-one cache RAM.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) Mouse Test Flexible Disk Controller Subsystem Test Internal Numeric Coprocessor Test Parallel Port Test Serial Port Test Hard Disk Controller Subsystem Test System Generation Plug and Play Configuration If a mouse is present, invokes a built-in mouse self-test of the mouse’s microprocessor and for stuck mouse buttons. Test failure causes an error code to display.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GX.07.xx) Beep Codes (BIOS version: GX.07.xx) If a terminal error occurs during POST, the system issues a beep code before attempting to display the error. Beep codes are useful for identifying the error when the system is unable to display the error message. Beep Pattern Numeric Code Description B4 This does not indicate an error. There is one short beep before system startup.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) HP/Phoenix BIOS (BIOS version: GJ.07.xx) This section gives an overview of the HP/Phoenix BIOS identified by the version number GJ.07.xx associated with the HP Vectra 500 Series models, HP Service part numbers: D3657-63001 and D3661-63001. The information in this section is divided into three main sub-sections: • Setup Program: with menu-driven context-sensitive help (in U.S. English only).
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Preferences Menu (BIOS version: GJ.07.xx) The Preferences Menu has the same menu structure as the Main Menu and Power Menu. This menu allows the user to set a password to prevent unauthorized access to the computer. To set a user password, the administrator password has to be set first. Configuration Menu (BIOS version: GJ.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Disabling a device in the Configuration Menu (for example, Serial port B in the diagram above) has the advantage of freeing the resources (such as IRQs and peripheral addresses). Disabling a device in the Security Menu disables the access, does not free the resources, but has the advantage of temporarily disabling the device without losing the configuration settings.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Summary Configuration Screen (BIOS version: GJ.07.xx) You can press while the initial “Vectra” logo screen is being displayed to run the Setup program (as described in the previous sub-sections). Alternatively, you can press to view the summary configuration screen. This is displayed for a few seconds only, but it is possible to “freeze” it so the configuration can be checked. Press the Pause/Break key to “freeze” the summary screen.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) I/O Addresses Used by the System (BIOS version: GJ.07.xx) Peripheral devices, accessory devices and system controllers are accessed via the system I/O space. The 64 KB of addressable I/O space comprises 8-bit and 16-bit I/O ports (these are registers that are located in the various system components).
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) BIOS I/O Port Map (BIOS version: GJ.07.xx) This section describes the HP BIOS port map. The next section provides more details about how the BIOS uses the system board components mentioned in the I/O port list.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) I/O Address Ports Function 03BC-03BF Parallel Port 1 03F0--03F5-03F7 Integrated Floppy Disk Controller 03F8-03FF Serial Port 1 03E8-03EF Serial Port 3 0CF8-0CFF Used for PCI Configuration1 0496-0497 HP Reserved 0678-067A Parallel Port if ECP Mode is Selected 0778-077A Parallel Port if ECP Mode is Selected 1. Bits These addresses are dedicated to configuration registers for PCI devices.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) The following table summarizes how the DMA channels are allocated. First DMA controller (used for 8-bit transfers) Channel 0 1 2 3 Function Available Available or ECP mode for parallel port Floppy disk I/O Available or ECP mode for parallel port Second DMA controller (used for 16-bit transfers) Channel 4 5-6 6-7 Function Cascade from first DMA controller Available Available Interrupt Controllers (BIOS version: GJ.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Power-On Self-Test (BIOS version: GJ.07.xx) This section describes the Power-On Self-Test (POST) routines, which are contained in the PC’s ROM BIOS, the error messages which can result, and the suggestions for corrective action. Each time the system is powered on, or a reset is performed, the POST is executed. The POST process verifies the basic functionality of the system components and initializes certain system parameters.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) POST Test Description System BIOS Tests LED Test Processor Test System (BIOS) ROM Test RAM Refresh Timer Test Interrupt RAM Test Shadow the System ROM BIOS Load CMOS Memory CMOS RAM Test Internal Cache Memory Test Tests the LEDs on the control panel. Tests the processor’s registers. Test failure causes the boot process to abort. Calculates an 8-bit checksum. Test failure causes the boot process to abort.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) System Board Tests Test External Cache Tests the level-two cache. A failure causes an error code to display and disables the external cache. Shadow SCSI ROM Tests for the presence of HP SCSI ROMs. If SCSI ROMs are detected, their contents are copied into the shadow RAM area. A failure will cause an error code to display. 8042 Self-Test Downloads the 8042 and invokes the 8042 internal self-test.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Tests of Flexible Disk Drive A Flexible Disk Controller Subsystem Test Tests for proper operation of the flexible disk controller. Test failure causes an error code to display. Coprocessor Tests Internal Numeric Coprocessor Test Checks for proper operation of the numeric coprocessor part of the processor. Test failure causes an error code to display.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Error Messages (BIOS version: GJ.07.xx) When the PC is switched on or reset, a power-on hardware test is performed. If an error occurs, an error message is displayed. NOTE: HP’s new-style BIOS does not display POST error codes (such as 910B). These were displayed in the BIOS of previous HP Vectra PCs.
4 Summary of the HP/Phoenix BIOS HP/Phoenix BIOS (BIOS version: GJ.07.xx) Message Corrective Action and/or Explanation Other An error message may be displayed and the PC may “hang” for 20 seconds and then beep. The POST is probably checking for a mass storage device which it cannot find and the PC is in Timeout Mode. After Timeout, run Setup to check the configuration. Beep Codes (BIOS version: GJ.07.
5 Video Controllers This chapter gives details of the three types of video subsystems used by the HP Vectra 500 Series computers. These video subsystems are: the SiS 6250 and S3 Trio 64 PnP video controllers, both of which are integrated on the system board, and the Matrox MGA Millennium video card.
5 Video Controllers SiS 6205 Video Controller SiS 6205 Video Controller The SiS 6205 video controller supports UMA architecture, and therefore no dedicated video memory is loaded on the system board. The shared frame buffer is located in the system DRAM and the memory access bus and memory data bus. The SiS 6205 video controller offers full compatibility with VGA. In addition, the features are enhanced beyond the Super VGA by hardware which accelerates graphical user interface operation in Windows 95.
5 Video Controllers SiS 6205 Video Controller HP Vectra 500 Series with the SiS 6205 Chip Video Controllers SIS 6205 Video Controller Hardware Acceleration of major graphics operations to speed up applications using graphical user interfaces (GUIs) Yes DRAM support 1 MB of 60 ns resident in main memory. Graphics Resolutions Up to 1280 x 1023 Pixel Clock (Max.) 135 MHz Upgradeable to: 2 MB by using the HP Setup program, or Using the HP Dynamic Video Feature, on page 118.
5 Video Controllers SiS 6205 Video Controller Using the HP Dynamic Video Feature To increase the amount of video memory using the HP Dynamic video feature, follow these steps: • Click the Start button. • Select Settings, then Control Panel. • Double-click the Display icon. • Click the HP Dynamic Video tab. • Drag the Video Memory slider from 1 MB to 2 MB. (The System memory value is automatically adjusted).
5 Video Controllers SiS 6205 Video Controller VESA Feature Connector (SiS 6205 Chip) The Video Electronics Standards Association (VESA) defines a standard video connector, variously known as the VESA feature connector, auxiliary connector, or pass-through connector. The integrated video controller supports an output-only VESA feature connector. This connector is integrated directly on the system board and is connected directly to the pixel data bus and the synchronization signals.
5 Video Controllers The Integrated Ultra VGA Video Controller The Integrated Ultra VGA Video Controller The Integrated Ultra VGA video controller is installed on the HP Vectra 500 Series PC models with part number D3657-63001.
5 Video Controllers The Integrated Ultra VGA Video Controller S3 Trio 64 Video Memory The S3 Trio 64 PnP integrated video subsystem has 1 MB of video DRAM preinstalled on the system board, and provides two sockets for the installation of a pair of 512KB video DRAM chips, to upgrade to video memory to 2 MB. The installed video memory capacity is detected automatically by the BIOS. Normally, the controller gives 32-bit video memory access, with 1 MB of video RAM fitted.
5 Video Controllers The Integrated Ultra VGA Video Controller Mode No. Standard Interface Type Resolution No. of Colors Vertical Refresh (Hz) Horizontal Refresh (kHz) Dot Clock (MHz) 03h VGA text 80 x 25 chars 16 70 31.5 25.175 03h+ VGA text 80 x 25 chars 16 70 31.5 28.322 04h VGA graph 320 x 200 4 70 31.5 25.175 05h VGA graph 320 x 200 4 70 31.5 25.175 06h VGA graph 640 x 200 2 70 31.5 25.175 07h VGA text 80 x 25 chars Mono 70 31.5 28.
5 Video Controllers The Integrated Ultra VGA Video Controller VESA Mode No. Extended Mode No. Interface Type Resolution No.
5 Video Controllers The Integrated Ultra VGA Video Controller VESA Mode No. Extended Mode No. Interface Type Resolution No.
5 Video Controllers The Integrated Ultra VGA Video Controller Extended Video Modes with 2 MB DRAM (S3 Trio 64) VESA Mode No. Extended Mode No. Interface Type Resolution No.
5 Video Controllers The Integrated Ultra VGA Video Controller VESA Connector The Video Electronics Standards Association (VESA) defines a standard video connector, variously known as the VESA feature connector, auxiliary connector, or pass-through connector. The integrated video controller supports an output-only VESA feature connector. This connector is integrated directly on the system board, and is connected directly to the pixel data bus and the synchronization signals.
5 Video Controllers Matrox MGA Millennium Video Controller Card Matrox MGA Millennium Video Controller Card The Matrox MGA Millennium PCI video controller is installed in a PCI expansion slot. Its on-card MGA-2064W processor communicates with the Pentium Pro processor along the PCI bus. The Matrox MGA Millennium video controller is installed on the HP Vectra 500 Series PC models with system board part number D3661-63001.
5 Video Controllers Matrox MGA Millennium Video Controller Card MGA Connectors The Video Electronics Standards Association (VESA) defines a standard video connector, variously known as the VESA feature connector, auxiliary connector, or pass-through connector. The video controller supports an output-only VESA feature connector in VGA mode. This connector is integrated on the PCI card, and is connected directly to the pixel data bus and the synchronization signals.
5 Video Controllers Matrox MGA Millennium Video Controller Card Available MGA Video Resolutions The number of colors supported is limited by the video card and the video memory. The resolution/refresh-rate combination is limited by a combination of the display, the graphics card, and the video memory. If you attempt to set the resolution or number of colors higher than is supported by the installed video memory, the screen refresh rate is lowered automatically, and image flicker becomes more noticeable.
5 Video Controllers Matrox MGA Millennium Video Controller Card The following table summarizes the video resolutions which are supported. Number of Colors 256 64 K Hi-Color 16.7 M True-Color 16.7 M True-Color Bits per Pixel 8 16 24 32 640 ✕ 480 2 MB, 120 Hz 800 ✕ 600 1024 ✕ 768 2 MB, 120 Hz 1152 ✕ 882 1 1280 ✕ 1024 1600 ✕ 12002 1.
5 Video Controllers Matrox MGA Millennium Video Controller Card MGA Video BIOS A feature of the Matrox MGA Millennium card is the capability to flash program the video BIOS. This is achieved as follows: 1 Set SW-1, on the Matrox card, to ON (BIOS unprotected). 2 Set the “Operating System” field in the Setup program to Others. 3 Run the updbios.bat command file (provided by HP), to execute the video BIOS flash program, progbios.exe, and the associated *.bin file.
5 Video Controllers DB15 Connector Pinout DB15 Connector Pinout The layout of the pins for the DB15 VGA Connector are the same for the three video controllers mentioned earlier in this section.
6 Aztech AT3300 Audio Fax/Data Modem Depending on the particular HP Vectra 500 Series PC model, there may be an Aztech AT3300 audio fax/data modem installed. This modem incorporates built-in advanced communication and audio telephony features, including a capability to perform simultaneous audio playback and recording, as well as hands-free communication.
6 Aztech AT3300 Audio Fax/Data Modem Introduction Introduction The Aztech AT3300 audio fax/data modem operates in Plug and Play mode, therefore the hardware settings should not conflict with those of any other devices on the system. The Windows 95 Device Manager can be used to check the type of modem and configuration installed on the PC. The built-in full duplex Speakerphone communications option delivered with the HP Vectra 500 Series PC offers a complete business solution.
6 Aztech AT3300 Audio Fax/Data Modem Introduction Communications Options As a data modem, the modem operates at line speeds of up to 28,800 bps. Error correction (V.42/MNP 2-4) and data compression (V.42 bis/MNP 5) maximize data transfer integrity and boost data throughput up to 115.2 kbps. The modem also operates in non-errorcorrecting mode. Extended “AT” commands provide data, fax class 1 and class 2, and MNP 10 functions, while using minimal external ROM, RAM, and optional NVRAM.
6 Aztech AT3300 Audio Fax/Data Modem Introduction • Fax modem send and receive rates of up to 14,400 bps. V.17/V.29/V.27ter and V21 channel 2, Group 3 Fax mode. WARNING • Full duplex speakerphone. • Enhanced AT, voice and class 1 & 2 fax commands. • Line quality monitoring retrain. • Recording of telephone conversation through the communication card. • Support for external speakers. • Tone or pulse dialing. In some countries, pulse dialing is not supported.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration European Firmware and Telephone Line Configuration The configuration of the Aztech AT3300 audio fax/data modem is specific to each country’s telephone standards. The following table shows the different AT3300 European firmware configuration and telephone line interface.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration Aztech AT3300 Localisation Utility The Aztech AT3300 Localisation Utility floppy disk automatically determines which firmware country code is configured on the Aztech AT3300 audio fax/data modem, and has the possibility to modify the configuration.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration SELECT THE COUNTRY: A B C D E F G H I J K L M Belgium Denmark Finland France Germany Italy Netherlands Norway Portugal Spain Sweden Switzerland United Kingdom Q Quit which country → 1 Enter the letter that corresponds to the country to be configured. The message, “Please wait, reprogramming the modem” will be displayed while the Audio Fax/Data Modem is reconfigured.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration 4 After installing and localizing the Aztech AT3300 audio fax/data modem, you must then re-install the Mediatrends Quip software, since its license requires the card’s identification. For details, see the Localization Instructions and Replacement Instructions notices which accompany the replacement card.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration Enter the following AT commands to verify or change the firmware country code: Modem Response Comments tests that the PC and modem can communicate. OK modem confirmation ATE1 enables character echo so that the modem commands appear on the screen. OK modem confirmation ATI5 shows the current country code. xxx current code configuration is displayed OK modem confirmation.
6 Aztech AT3300 Audio Fax/Data Modem European Firmware and Telephone Line Configuration 142 English
Index A AT commands, 141 audio data/fax modem configuration, 137–141 current firmware country code, 138 European firmware, 137 features, 135–136 firmware code, 137 firmware country code, 137 jumper block color, 137 Localisation Utility, 138–140 localize firmware code using HyperTerminal, 140 pulse dialing, 137 audio fax/data modem communications options, 135 introduction, 134 line speeds, 135 service providers, 134 standards, 134 telephone line, 135 Aztech AT3300 current firmware country code, 138 firmware
Index R rear panel display connector, 24 keyboard socket, 24 mouse socket, 24 parallel device socket, 24 serial device connectors, 24 rear panel connectors minitower and desktop, 24 S S3 Trio 64 extended VGA modes (1 MB), 122 extended VGA modes (2 MB), 125 standard VGA modes, 121 video memory, 121 video modes, 121 S3 Trio 64 chip video controller summary, 120 service part number D4051-63001Super I/O chip (NS 87308 and NS 87307) keyboard and mouse controller, 55 service part number D4051-63001 advanced powe
Index T Typical Windows 95 resolutions S3 Trio 64 video controller, 125 SiS 6205 video controller, 118 U UMA upgrading video memory, 117 using the HP Dynamic video feature, 118 Unified Memory Architecture system board overview, 28 V video controllers Integrated Ultra VGA, 120–125 Matrox MGA Millennium, 127–131 SiS 6205, 116–118 video modes extended (S3 Trio 64) VGA modes (1 MB), 122 extended (S3 Trio 64) VGA modes (2 MB), 125 S3 Trio 64, 121 standard (S3 Trio 64) VGA modes, 121 video subsystem S3 Trio 64,
Index 146
