HP StorageWorks Fabric OS 5.0.0 Command Reference Guide (AA-RW1MA-TE, May 2005)

Fabric OS 5.0.0 command reference guide 73
Tests ASIC-pair central memory operation.
Synopsis
centralmemorytest [--slot slotnumber][-passcnt count][-datatype
type][-ports itemlist][-seed value]
Availability
admin
Description
Use this command to execute an address and data bus verification of the ASIC SRAMs that serve as the
central memory.
NOTE: This command cannot be executed on an enabled switch. You must first disable the switch using
the switchDisable command.
The test consists of six subtests, each described next.
Built-in self-repair subtest
The built-in self-repair subtest executes the built-in self-repair (BISR) circuitry in each ASIC. The BISR
executes its own BIST, and cells found to be bad are replaced by redundant rows provided in each SRAM
in the ASIC. Once the cells are replaced, the BIST is executed again.
The firmware sets up the hardware for the BISR/BIST operation and checks the results. If the done bit in
each SRAM is not set within a time-out period, it reports the DIAG-CMBISRTO. If any of the SRAMs within
the ASIC fails to map out the bad rows, its fail bit is set and the DIAG-CMBISRF error generated.
Data read/write subtest
The data write/read subtest executes the address and data bus verifications by running a specified unique
ramp pattern D to all SRAMs in all ASICs in the switch. When all SRAMs are written with pattern D, the
SRAMs are read and compared against the data previously written. This procedure is repeated with the
complemented pattern ~D to ensure that each data bit is toggled during the test.
The default pattern used (by POST also) is a QUAD_RAMP with a seed value of 0.
ASIC-to-ASIC connection subtest
NOTE: This subtest is not available on 2 Gb/s-capable switches.
The ASIC-to-ASIC connection subtest verifies that any port can read the data from any of the ASICs in the
switch, thus verifying both the logic transmitting and receiving the data and the physical transmit data
paths on the main board connecting all the ASICs to each other.
The test method is as follows:
1. Fill the central memory of all ASICs with unique frames.
2. Set up the hardware such that each ASIC is read by all of the ports in the switch. Data received is
compared against the frame written into the ASIC.
• Port 0 reads the central memory in ASIC 0.
centralMemoryTest