DDR3 memory technology

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Figure 5: Diagram of a traditional 2P uniform memory architecture
CPUCPU
System Chipset
Front Side BusFront Side Bus
Memory Channels (4)
Intel 2P Memory Architecture
with Front Side Bus
This architecture gave each memory channel a maximum raw bandwidth of 9.6 GB/s for systems
supporting PC2-6400 fully buffered DIMMs. The memory channels of systems that use registered
DIMMs can support a maximum bandwidth of 6.4 GB/s. With four memory channels per system, the
theoretical maximum memory bandwidth for these systems is 38.4 GB/s and 25.6 GB/s,
respectively. There are, however, factors that limit the achievable throughput:
• The maximum bandwidth of the front side bus became a performance choke point.
• Larger memory footprints required fully buffered DIMMS, which increased memory latency and
decreased memory throughput and performance.
DDR3 and NUMA systems architecture
Although they vary slightly in their implementation details, NUMA architectures share a common
design concept. With NUMA, each processor in the system has separate memory controllers and
memory channels. In addition to increasing the total number of memory controllers and memory
channels in the system, each processor accesses its attached memory directly. This eliminates the
bottleneck of the front side bus and reduces latency. A processor accesses the system memory
attached to a different processor through high-speed serial links that connect the primary system
components. In Intel-based systems, it is the QuickPath Interconnect (QPI). For AMD-based systems, it
is the HyperTransport technology. Beginning with the HP ProLiant G6, all HP ProLiant servers use
DDR3 memory to help increase memory throughput. Figure 6 shows how the NUMA architecture
looks for a typical ProLiant 2P server.