DDR3 memory technology

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To compensate for this skew, the memory controller must adjust its timing to lock in the bits from each
DRAM at an appropriately delayed interval. This process is known as read leveling. These delays also
vary slightly from one DRAM and DIMM to another. The memory controller must determine them
empirically and then program them each time that the system reboots. This process is known as
memory training. For memory writes, this scenario reverses, and the memory controller must delay the
presentation of different sets of data bits to the bus to match the time when each DRAM is ready to
receive them.
On-die Termination
Electrical circuits that carry signals need to be terminated with resistors to damp electrical reflections
and to improve overall signal integrity. Earlier memory standards had memory termination on the
system board. On-die termination puts the resistors on the DRAMs themselves, increasing their
effectiveness by placing them at the end of the memory bus circuits. With DDR3 memory, the number
of possible termination values is significantly greater than for DDR2. Just as important, the memory
controller now empirically sets the termination values during POST based on the configuration of the
DIMM module itself (number of ranks) and its position on the memory channel. Both of these
refinements contribute to the signal integrity improvements necessary to support the faster DDR3
speeds.
Address parity checking on RDIMMs
In DDR2, address parity detection was an optional feature. With DDR3, it’s now standard. On DDR3
RDIMMs, the register chip performs a parity check on the DRAM address lines and compares it to the
parity bit from the memory controller. This process detects potential addressing errors. Although
address parity checking cannot correct addressing errors, it does stop the controller from writing data
to an incorrect DRAM address, preventing silent data corruption. Unbuffered DIMMs do not support
address parity checking because they do not have a register.
Integrated DIMM temperature sensor
DDR3 memory modules have built-in temperature sensors accurate to ½ °C located in the center of
each DIMM (Figure 4). HP engineers have taken advantage of the information these DIMM
temperature sensors deliver by integrating it into Sea of Sensors fan control technology controlled by
the iLO management processor found in all current ProLiant servers.