Technical Reference Guide HP Compaq dx7200 and dc7600 Series Business Desktop Computers Document Part Number: 391758-001 January 2005 This document provides information on the design, architecture, function, and capabilities of the HP Compaq dx7200 and dc7600 Series Business Desktop Computers. This information may be used by engineers, technicians, administrators, or anyone needing detailed information on the products covered.
© Copyright 2005 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. Microsoft, MS-DOS, Windows, and Windows NT are trademarks of Microsoft Corporation in the U.S. and other countries. Intel, Pentium, Intel Inside, and Celeron are trademarks of Intel Corporation in the U.S. and other countries. Adobe, Acrobat, and Acrobat Reader are trademarks or registered trademarks of Adobe Systems Incorporated.
Contents 1 Introduction 1.1 About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Online Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Hardcopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Additional Information Sources . . . . . . . . . . . . . . . . . .
Contents 3 Processor/Memory Subsystem 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Processor Upgrading . . . . . . . . . . . . . .
Contents 5.6 5.7 5.8 5.9 5.5.5 Parallel Interface Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard/Pointing Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Keyboard Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Pointing Device Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 8 BIOS ROM 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 8.2 ROM Flashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 8.2.1 Upgrading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 8.2.2 Changeable Splash Screen . . . . . . . . . .
1 Introduction 1.1 About this Guide This guide provides technical information about HP Compaq dx7200 and dc7600 series personal computers that feature the Intel Pentium 4 processor and the Intel 945G chipset. This document describes in detail the system's design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.
Introduction 1.3 Model Numbering Convention The model numbering convention or HP systems is as follows: 1-2 www.hp.
Introduction 1.4 Serial Number The unit's serial number is located on a sticker placed on the exterior cabinet. The serial number is also written into firmware and may be read with HP Diagnostics or Insight Manager utilities. 1.5 Notational Conventions The notational guidelines used in this guide are described in the following subsections. 1.5.1 Values Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter “h.
Introduction 1.6 Common Acronyms and Abbreviations Table 1-1 lists the acronyms and abbreviations used in this guide.
Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Ch Channel, chapter cm centimeter CMC cache/memory controller CMOS complimentary metal-oxide semiconductor (configuration memory) Cntlr controller Cntrl control codec 1. coder/decoder 2. compressor/decompressor CPQ Compaq CPU central processing unit CRIMM Continuity (blank) RIMM CRT cathode ray tube CSM 1. Compaq system management 2.
Introduction Table 1-1 Acronyms and Abbreviations 1-6 Acronym or Abbreviation Description ESCD Extended System Configuration Data (format) EV Environmental Variable (data) ExCA Exchangeable Card Architecture FIFO first in/first out FL flag (register) FM frequency modulation FPM fast page mode (RAM type) FPU Floating point unit (numeric or math coprocessor) FPS Frames per second ft Foot/feet GB gigabyte GMCH Graphics/memory controller hub GND ground GPIO general purpose I/O G
Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Kb/KB kilobits/kilobytes (x 1024 bits/x 1024 bytes) Kb/s kilobits per second kg kilogram KHz kilohertz kV kilovolt lb pound LAN local area network LCD liquid crystal display LED light-emitting diode LPC Low pin count LSI large scale integration LSb/LSB least significant bit/least significant byte LUN logical unit (SCSI) m Meter MCH Memory controller hub MMX multimedia extensions MPEG Mot
Introduction Table 1-1 Acronyms and Abbreviations 1-8 Acronym or Abbreviation Description PC Personal computer PCA Printed circuit assembly PCI peripheral component interconnect PCI-E PCI Express PCM pulse code modulation PCMCIA Personal Computer Memory Card International Association PEG PCI express graphics PFC Power factor correction PIN personal identification number PIO Programmed I/O PN Part number POST power-on self test PROM programmable read-only memory PTR pointer R
Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description SIMD Single instruction multiple data SIMM single in-line memory module SMART Self Monitor Analysis Report Technology SMI system management interrupt SMM system management mode SMRAM system management RAM SPD serial presence detect SPDIF Sony/Philips Digital Interface (IEC-958 specification) SPN Spare part number SPP standard parallel port SRAM static RAM SSE Streaming SIMD extensions STN super
Introduction Table 1-1 Acronyms and Abbreviations 1-10 Acronym or Abbreviation Description VDC Volts direct current VESA Video Electronic Standards Association VGA video graphics adapter VLSI very large scale integration VRAM Video RAM W watt WOL Wake-On-LAN WRAM Windows RAM ZF zero flag ZIF zero insertion force (socket) www.hp.
2 System Overview 2.1 Introduction The HP Compaq dx7200 and dc7600 Series Business Desktop Computers (Figure 2-1) deliver an outstanding combination of manageability, serviceability, and compatibility for enterprise environments. Based on the Intel Pentium 4 processor with the Intel 945G Chipset, these systems emphasize performance along with industry compatibility. These models feature architectures incorporating the PCI bus.
System Overview 2.2 Features The following standard features are included on all series inless otherwise indicated: 2-2 ■ Intel Pentium 4 processor in LGA775 (Socket T) package ■ Integrated graphics controller ■ PC2-4200 DIMM support on all models ■ Serial ATA (SATA) interfaces supporting transfer rates up to 3.0 Gbps ■ Parallel ATA (PATA or Ultra ATA 100/66/33) interface ■ PCI 2.3 and PCI Express interfaces ■ Hard drive fault prediction ■ Eight USB 2.
System Overview Table 2-1 shows the differences in features between the different PC series based on form factor: Table 2-1 Difference Matrix by Form Factor USDT SFF ST MT CMT Series dc7600 dc7600 dx7200 dx7200 dc7600 System Board Type custom custom custom µATX µATX Optional [1] Standard Standard Standard Standard 3 3 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 1 1 2 1 2 1 4 2 4 2 1 [2] 0 1 [2] [3] 1 [3] 1 [2] [3] 1 [3] 1 [4] 1 1 [4] 1 2 full-height 2 or 4
System Overview 2.3 Mechanical Design This guide covers five form factors: ■ Ultra Slim Desktop (USDT)—Very slim design that can be used in a tradition desktop (horizontal) orientation or as a small tower mounted in the supplied tower stand. ■ Small Form Factor (SFF)—A small-footprint desktop requiring minimal desk space. ■ Slim Tower (ST)—Slim design that can be used in a tradition desktop (horizontal) orientation or as a small tower mounted in the supplied tower stand.
System Overview 2.3.1 Cabinet Layouts Front Views Figure 2-2 shows the front panel components of the Ultra Slim Desktop (USDT) format factor. Item Description Item Decription 1 MultiBay device bay 5 USB ports 7, 8 2 MultiBay device eject lever 6 Power LED 3 Microphone audio In jack 7 MultiBay device / HD activity LED 4 Headphone audio Out jack 8 Power button Figure 2-2. HP Compaq dc7600 USDT Front View Technical Reference Guide www.hp.
System Overview Figure 2-3 shows the front panel components of the Small Form Factor (SFF). Item Description Item Decription 1 Diskette drive activity LED 7 Microphone audio In jack 2 Diskette drive media door 8 Headphone audio Out jack 3 CD-ROM drive acitvity LED 9 USB ports 7, 8 4 Diskette drive eject button 10 Hard drive activity LED 5 CD-ROM media tray 11 Power LED 6 CD-ROM drive open/close button 12 Power button Figure 2-3. HP Compaq dc7600 SFF Front View 2-6 www.hp.
System Overview Figure 2-4 shows the front panel components of the Slim Tower (ST) form factor. Item Description Item Decription 1 Microphone audio in jack 7 Diskette drive activity LED 2 Headphone audio out jack 8 Diskette media door 3 USB ports 7, 8 9 CD-ROM drive acitvity LED 4 hard drive activity LED 10 Diskette drive eject button 5 Power LED 11 CD-ROM media tray 6 Power button 12 CD-ROM drive open/close button Figure 2-4.
System Overview Figure 2-5 shows the front panel components of the microtower (uT) form factor. Item Description Item Decription 1 CD-ROM drive 7 CD-ROM drive open/close button 2 CD-ROM drive activity LED 8 Power button 3 Diskette drive media door 9 Power LED 4 Diskette drive activity LED 10 Hard drive activity LED 5 Diskette drive eject button 11 Headphone audio Out jack 6 USB ports 7, 8 12 Microphone audio In jack Figure 2-5. HP Compaq dx7200 MT Front View 2-8 www.hp.
System Overview Figure 2-6 shows the front panel components of the Convertable Minitower (CMT) form factor. Item Description Item Decription 1 CD-ROM drive 7 CD-ROM drive open/close button 2 CD-ROM drive activity LED 8 Power button 3 Diskette drive media door 9 Power LED 4 Diskette drive activity LED 10 USB ports 7, 8 5 Diskette drive eject button 11 Headphone audio Out jack 6 Hard drive activity LED 12 Microphone audio In jack Figure 2-6.
System Overview Rear Chassis Connections Table 2-2 describes the signal connections available on the rear panels of the dx7200 and dc7600 models. Note that not all connectors listed are provided on all form factors. Table 2-2 Rear Panel Signal Connections Connector & Icon Description AC input connector. (no icon) PS/2 female connector (color-coded purple) for keyboard interface. PS/2 female connector (color-coded green) for mouse interface Universal serial bus (USB) connector for USB 2.
System Overview 2.3.2 Chassis Layouts This section describes the internal layouts of the chassis. For detailed information on servicing the chassis refer to the multimedia training and/or the maintenance and service guide for these systems. UIltra Slim Desktop Chassis The Ultra Slim Desktop (USDT) chassis used for the HP Compaq dc7600 models uses a compact, space-saving form factor.
System Overview Small Form Factor / Slim Tower Chassis The chassis layouts for the Small Form Factor (SFF) used for the HP Compaq dc7600 models and the Slim Tower (ST) used for the HP Comapq dx7200 models are shown in Figure 2-8. Features include: ■ Tilting drive cage assembly for easy access to processor and memory sockets ■ Two configuration available: ❏ ❏ Without card cage: ◆ Two half-height, full length PCI 2.
System Overview Microtower Chassis Figure 2-9 shows the layout for the Microtower (MT) chassis used for the HP Compaq dx7200 models. Features include: ■ Externally accessible drive bay assembly. ■ Easy access to expansion slots and all socketed system board components. 1 2 3 4 5 6 q 7 9 8 Item Description Item Description 1 Power supply assembly 7 Speaker 2 Processor socket 8 PCI 2.
System Overview Convertible Minitower Figure 2-10 shows the layout for the Convertible Minitower (CMT) chassis in the minitower configuration used for HP Compaq dc7600 models. Features include: ■ Externally accessible drive bay assembly may be configured for minitower (vertical) or desktop (horizontal) position. ■ Easy access to expansion slots and all socketed system board components.
System Overview 2.3.3 Board Layouts Figures 2-11 through 2-13 show the system and expansion boards for these systems. Figure the 2-9 shows the layout for the USDT systems board, which is a custom board specifically designed for that particular form factor.
System Overview 123 4 5 6 7 8 f d s a p o i u 9 - y t re w q Item Description Item Description 1 Serial port B header 13 Power button, power LED, HD LED header 2 CMOS clear button 14 Front panel audio header 3 SATA #0 header (dark blue) 15 Chassis speaker connector 4 SATA #1 header (white) 16 Front panel USB port connector 5 Password clear jumper 17 DIMM sockets (4) 6 PCI Express x1 slot 18 Diskette drive connector 7 PCI Express x16 graphics/reversed-layout SDVO slot 19
System Overview 1 2 34 1 z k l 5 6 7 j h g f d s 8 9 - a p o iuyt r PCI Expansion Board [1] e w q System Board Item Description Item Description 1 PCI 2.
System Overview 2.4 System Architecture The systems covered in this guide feature an architecture based on the Intel Pentium 4 processor and the Intel 945G chipset (Figure 2-14). These systems allow processor upgrading with the Intel Pentium 4 family and offer flexibility in expansion capabilities. All systems covered in this guide include the following key components: ■ Intel Pentium 4 with Hyper-Threading technology, 32-KB L1 cache and 1-MB L2 cache.
System Overview Pentium 4 Processor 945G Chipset RGB Monitor PCI Express x16 slot (PEG)[1] SATA2 Hard Drive Graphics Cntlr. 945G GMCH SDRAM Cntlr PCI Exp. PEG I/F [1] DMI DMI SATA I/F USB I/F MultiBay Device [2] CD-ROM HD Audio Subsystem 82801 ICH8 PATA I/F Ch A DDR2 SDRAM Ch B DDR2 SDRAM USB Ports 1-8 Serial I/F [1] Parallel I/F [1] SCH5307 I/O Cntlr. LPC I/F Kybd-Mouse I/F Diskette I/F Audio I/F PCI Cntlr. Floppy Keyboard PCI 2.
System Overview 2.4.1 Intel Pentium 4 Processor The models covered in this guide feature the Intel Pentium 4 processor with Hyper-Threading technology. This processor is backward-compatible with software written for the Pentium III, Pentium II, Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors.
System Overview 2.4.2 Chipset The chipset consists of a Graphics Memory Controller Hub (GMCH), an enhanced I/O controller hub (ICH), and a firmware hub (FWH). Table 2-4 compares the functions provided by the chipsets. Table 2-4 Chipset Components Components Function 82945G GMCH Intel Graphics Media Accelerator 950 (integrated graphics controller) PCI Express x16 graphics interface (945G only) SDRAM controller supporting unbuffered, non-ECC PC2-4200 DDR2 DIMMs 533-, or 800-MHz FSB 82801GB ICH8 PCI 2.
System Overview 2.4.3 Support Components Input/output functions not provided by the chipset are handled by other support components. Some of these components also provide “housekeeping” and various other functions as well. Table 2-5 shows the functions provided by the support components.
System Overview 2.4.5 Mass Storage All models support at least two mass storage devices, with one being externally accessible for removable media. These systems provide one, two, or four SATA interfaces and one PATA interface. These systems may be preconfigured or upgraded with a 40-, 80-, or 160-GB SATA hard drive and one removable media drive such as a CD-ROM drive. USDT systems also provide one MultiBay interface. 2.4.
System Overview 2.4.9 Graphics Subsystem These systems use the 82945G GMCH component that integrates an Intel graphics controller that can drive an external VGA monitor. The integrated graphics controller (IGC) features a 333-MHz core processor and a 400-MHz RAMDAC. The controller implements Dynamic Video Memory Technology (DVMT 3.0) for video memory. Table 2-6 lists the key features of the integrated graphics subsystem.
System Overview 2.5 Specifications This section includes the environmental, electrical, and physical specifications for the systems covered in this guide. Where provided, metric statistics are given in parenthesis. Specifications are subject to change without notice. Table 2-7 Environmental Specifications (Factory Configuration) Parameter Operating Non-operating Ambient Air Temperature 50o to 95o F (10o to 35o C, max. rate of change < 10°C/Hr) -24o to 140o F (-30o to 60o C, max.
System Overview Table 2-9 Physical Specifications Parameter USDT ST SFF MT CMT [3] Height 2.95 in (7.49 cm) 13.3 in (33.78 cm) 3.95 in (10.03 cm) 14.5 in (36.8 cm) 17.65 in (44.8 cm) Width 12.4 in (31.5 cm) 3.95 in (10.03 cm) 13.3 in (33.78 cm) 6.88 in 17.5 cm) 6.60 in (16.8 cm) Depth 13.18 in (33.48 cm) 14.9 in (37.85 cm) 14.9 in (37.85 cm) 16.31 in (41.1 cm) 17.8 in (45.21 cm) Weight [1] 13.2 lb [2] (6.0 kg) [2] 19.5 lb (8.8 kg) 19.5 lb (8.8 kg) 23.8 lb (10.8 kg) 32.5 lb (14.
System Overview Table 2-10 Diskette Drive Specifications Parameter Measurement Media Type 3.5 in 1.44 MB/720 KB diskette Height 1/3 bay (1 in) Bytes per Sector 512 Sectors per Track: High Density Low Density 18 9 Tracks per Side: High Density Low Density 80 80 Read/Write Heads 2 Average Access Time: Track-to-Track (high/low) Average (high/low) Settling Time Latency Average Technical Reference Guide 3 ms/6 ms 94 ms/169 ms 15 ms 100 ms www.hp.
System Overview Table 2-11 Optical Drive Specifications Parameter 48x CD-ROM 48/24/28x CD-RW Drive Interface Type IDE IDE Media Type (reading) Mode 1,2, Mixed Mode, CD-DA, Photo CD, Cdi, CD-XA Mode 1,2, Mixed Mode, CD-DA, Photo CD, Cdi, CD-XA Media Type (writing) N/a CD-R, CD-RW Transfer Rate (Reads) 4.8 Kb/s (max sustained) CD-ROM, 4.8 Kb/s; CD-ROM/CD-R, 1.5-6 Kb/s Transfer Rate (Writes): N/a CD-R, 2.4 Kbps (sustained); CD-RW, 1.
System Overview Table 2-12 Hard Drive Specifications Parameter 40 GB 80 GB 160 GB Drive Size 3.5 in 3.5 in 3.5 in Interface SATA SATA SATA 300 Gb/s 300 Gb/s 300 Gb/s Yes Yes Yes 1.2 ms 8.0 ms 18 ms 0.8 ms 9.0 ms 17 ms 0.
System Overview 2-30 www.hp.
3 Processor/Memory Subsystem 3.1 Introduction This chapter describes the processor/memory subsystem. These systems feature the Intel Pentium 4 processor and the 945G chipset (Figure 3-1). The dx7200 and dc7600 models support PC2-4200 DDR2 DIMMs. Pentium 4 Processor FSB I/F 82945G GMCH XMM1 XMM2 [1] Ch A DIMM Ch A DIMM Ch B DIMM Ch B DIMM XMM3 XMM4 SDRAM Cntrl Note: [1] SFF, ST, and CMT models only. Figure 3-1.
Processor/Memory Subsystem 3.2 Pentium 4 Processor These systems each feature an Intel Pentium 4 processor in a FC-LGA775 package mounted with a heat sink in a zero-insertion force socket. The mounting socket allows the processor to be easily changed for servicing and/or upgrading. 3.2.1 Processor Overview The Intel Pentium 4 processor represents the latest generation of Intel's IA32-class of processors.
Processor/Memory Subsystem Figure 3-2 illustrates the internal architecture of the Intel Pentium 4 processor. Pentium 4 Processor Branch Prediction 16-K Execution Trace Cache CPU Rapid Exe. Eng. ALUs Core speed Pentium Type P4 670 P4 660 P4 650 P4 640 P4 630 Out-of-Order Core 128-bit Integer FPU L2 Adv.. Transfer Cache FSB I/F ALU Speed (Core speed x2) Core Speed 3.80 GHz 3.60 GHz 3.40 GHz 3.20 GHz 3.00 GHz 8-K L1 L1 Cache Data Cache ALU Speed 7.6 GHz 7.2 GHz 6.8 GHz 6.4 GHz 6.
Processor/Memory Subsystem 3.3 Memory Subsystem All models support PC2-4200 DDR2 (533-MHz) memory. The USDT form factor supports up to 3 gigabytes of memory while the SFF, ST, MT, and CMT form factors support up to 4 gigabytes of memory. DDR SDRAM “PCxxxx” reference designates bus bandwidth (i.e., a PC2700 DIMM can, ✎ The operating at a 333-MHz effective speed, provide a throughput of 2700 MBps (8 bytes × 333MHz)).
Processor/Memory Subsystem Table 3-1 shows suggested memory configurations for these systems. NOTE: Table 3-1 does not list all possible configurations. Balanced-capacity, dual-channel loading yields best performance. Table 3-1.
Processor/Memory Subsystem The SPD address map is shown in Table 3-2. Table 3-2 SPD Address Map (SDRAM DIMM) Byte Description Notes Byte Description Notes 0 No. of Bytes Written Into EEPROM [1] 25 Min. CLK Cycle Time at CL X-2 [7] 1 Total Bytes (#) In EEPROM [2] 26 Max. Acc. Time From CLK @ CL X-2 [7] 2 Memory Type 27 Min. Row Prechge. Time [7] 3 No. of Row Addresses On DIMM 28 Min. Row Active to Delay [7] 4 No. of Column Addresses On DIMM 29 Min.
Processor/Memory Subsystem Figure 3-3 shows the system memory map. FFFF FFFFh 4 GB High BIOS Area FFE0 0000h DMI/APIC Area F000 0000h PCI Memory Area IGC (1-32 MB) TSEG Main Memory Area Top of DRAM Main Memory 0100 0000h 16 MB 00FF FFFFh Main Memory 0010 0000h 000F FFFFh BIOS Extended BIOS Expansion Area Legacy Video DOS Compatibilty Area 1 MB 640 KB Base Memory 0000 0000h locations in memory are cacheable. Base memory is always mapped to DRAM.
Processor/Memory Subsystem 3-8 www.hp.
4 System Support 4.1 Introduction This chapter covers subjects dealing with basic system architecture and covers the following topics: ■ PCI bus overview (4.2), page 4-1 ■ System resources (4.3), page 4-11 ■ Real-time clock and configuration memory (4.4), page 4-19 ■ System management (4.5), page 4-20 ■ Register map and miscellaneous functions (4.
System Support 82945G GMCH Memory Cntlr Function PCI Bus 0 Integrated Graphics Controller RGB Monitor Host-PCI Exp. Bridge PCI Express x16 graphics slot [1] Host-DMI Bridge DMI Link 82801 ICH8 DMI PCI Bus 1 PCI 2.3 Bridge Function PCI Exp. Port 1 Function PCI Exp. Port 2 Function IDE USB I/F HD Audio SATA LPC Cntlr Bridge Cntlr Cntlr Cntlr Function Function Function Function Function NIC Cntlr PCI Express x1 slot [1] PCI 2.3 slot(s) Notes: Only implemented functions are shown.
System Support Configuration Cycles Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus specification Rev. 2.3) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configuration space of a PCI device.
System Support Table 4-1 shows the standard configuration of device numbers and IDSEL connections for components and slots residing on a PCI 2.3 bus. Table 4-1 PCI Component Configuration Access PCI Component Notes Function # Device # PCI Bus # 0 1 0 28 28 2 0 0 0 0 0 32 0 0 1 2 3 0 1 2 3 7 2 3 0 0 1 2 3 4 5 0 30 31 31 31 31 29 29 29 29 29 30 30 8 28 28 28 28 28 28 27 0 0 0 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 4 8 AD20 82945G GMCH: Host/DMI Bridge Host/PCI Expr.
System Support The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header. 31 24 23 16 15 8 7 0 Index FCh 31 24 23 Device-Specific Area Min. GNT Int. Pin Int.
System Support Table 4-3. PCI Bus Mastering Devices Device REQ/GNT Line Note PCI Connector Slot 1 REQ0/GNT0 PCI Connector Slot 2 REQ1/GNT1 [1] PCI Connector Slot 3 REQ3/GNT3 [2] PCI Connector Slot 4 REQ4/GNT4 [2] NOTE: [1] SFF, ST, MT, and CMT form factors only. [2] CMT form factor with PCI expansion board PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification.
System Support Link Layer The link layer provides data integrity by adding a sequence information prefix and a CRC suffix to the packet created by the transaction layer. Flow-control methods ensure that a packet will only be transferred if the receiving device is ready to accomodate it. A corrupted packet will be automatically re-sent. Physical Layer The PCI Express bus uses a point-to-point, high-speed TX/RX serial lane topology that can be scalable as to the the end point’s requirements.
System Support For a PCI Express x16 transfer, a lane will be re-used for the transfer of every17th byte. The mux-demux process provided by the physical layer is transparent to the other layers and to software/drivers. The SFF, ST, MT, and CMT form factors provide two PCI Express slots: a PCI Express x16 (16-lane) slot specifically designed for a graphics controller, and a general purpose PCI Express x1 (1-lane) slot. 4.2.
System Support 4.2.6 PCI Connectors PCI 2.3 Connector A1 B2 A49 A52 A62 B49 B52 B62 Figure 4-5. PCI 2.3 Bus Connector (32-Bit, 5.0-volt Type) Table 4-5. PCI 2.3 Bus Connector Pinout Pin B Signal A Signal Pin B Signal A Signal Pin B Signal A Signal 01 -12 VDC TRST- 22 GND AD28 43 +3.3 VDC PAR 02 TCK +12 VDC 23 AD27 AD26 44 C/BE1- AD15 03 GND TMS 24 AD25 GND 45 AD14 +3.3 VDC 04 TDO TDI 25 +3.
System Support PCI Express Connectors A1 A11 A12 A18 x1 Connector A82 x16 Connector B1 B11 B82 B12 Figure 4-6. PCI Express Bus Connectors Table 4-6.
System Support 4.3 System Resources This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants. 4.3.1 Interrupts The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI instructions.
System Support 8259 Mode The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259-equivalent logic. Table 4-7 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first. Table 4-7.
System Support APIC Mode The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages: ■ Eliminates the processor's interrupt acknowledge cycle by using a separate (APIC) bus ■ Programmable interrupt priority ■ Additional interrupts (total of 24) The APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI devices.
System Support Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped registers. These registers are listed in Table 4-8. Table 4-8. Maskable Interrupt Control Registers I/O Port 020h 021h 0A0h 0A1h Register Base Address, Int. Cntlr. 1 Initialization Command Word 2-4, Int. Cntlr. 1 Base Address, Int. Cntlr. 2 Initialization Command Word 2-4, Int. Cntlr. 2 The initialization and operation of the interrupt control registers follows standard AT-type protocol.
System Support The NMI Status Register at I/O port 061h contains NMI source and status data as follows: NMI Status Register 61h Bit 7 6 5 4 3 2 1 0 Function NMI Status: 0 = No NMI from system board parity error.
System Support 4.3.2 Direct Memory Access Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks. section describes DMA in general.
System Support DMA Page Registers The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit) address for the DMA channels. Table 4-10 lists the page register port addresses. Table 4-10.
System Support The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The refresh rate is 128 refresh cycles in 2.038 ms. DMA Controller Registers Table 4-11 lists the DMA Controller Registers and their I/O port addresses. Note that there is a set of registers for each DMA controller. Table 4-11.
System Support 4.4 Real-Time Clock and Configuration Memory The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 component and is MC146818-compatible. As shown in the following figure, the 82801 ICH8 component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area.
System Support 4.4.2 Standard CMOS Locations Table 4-12 describes standard configuration memory locations 0Ah-3Fh. These locations are accessible through using OUT/IN assembly language instructions using port 70/71h or BIOS function INT15, AX=E823h. Table 4-12.
System Support Power-On / Setup Password These systems include a power-on and setup passwords, which may be enabled or disabled (cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH8 that is checked during POST. The password is stored in configuration memory (CMOS) and if enabled and then forgotten by the user will require that either the password be cleared (preferable solution and described below) or the entire CMOS be cleared (refer to section 4.4.1).
System Support Level 0—Cover removal indication is essentially disabled at this level. During POST, status bit is cleared and no other action is taken by BIOS. Level 1—During POST the message “The computer's cover has been removed since the last system start up” is displayed and time stamp in CMOS is updated.
System Support 4.5.3 System Status These systems provide a visual indication of system boot, ROM flash, and operational status through the power LED and internal speaker, as described in Table 13. d . Table 4-13. System Operational Status LED Indications System Status PowerLED Beeps [2] S0: System on (normal operation) Steady green None None S1: Suspend Blinks green @ .5 Hz None None S3: Suspend to RAM Blinks green @ .
System Support 4.6 Register Map and Miscellaneous Functions This section contains the system I/O map and information on general-purpose functions of the ICH8 and I/O controller. 4.6.1 System I/O Map Table 4-14 lists the fixed addresses of the input/output (I/O) ports. Table 4-14 System I/O Map I/O Port Function 0000..001Fh DMA Controller 1 0020..002Dh Interrupt Controller 1 002E, 002Fh Index, Data Ports to SCH5307 I/O Controller (primary) 0030..003Dh Interrupt Controller 0040..
System Support 4.6.2 SCH5307 I/O Controller Functions The SCH5307 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions uses indexed ports unique to the SCH5307.
System Support The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface (logical device) is initiated by firmware selecting logical device number of the 47B347 using the following sequence: 1. Write 07h to I/O register 2Eh. 2. Write value of logical device to I/O register 2Fh. 3. Write 30h to I/O register 2Eh. 4.
5 Input/Output Interfaces 5.1 Introduction This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter: 5.2 ■ PATA/SATA interface (5.2), page 5-1 ■ Diskette drive interface (5.3), page 5-7 ■ Serial interfaces (5.4), page 5-12 ■ Parallel interface (5.
Input/Output Interfaces IDE Configuration Registers The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #31, function #1) are listed in Table 5-1. Table 5-1. EIDE PCI Configuration Registers (82801) PCI Conf. Addr. Register 8086h 0F..
Input/Output Interfaces IDE Bus Master Control Registers The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. Table 5-2.
Input/Output Interfaces Table 5-3.
Input/Output Interfaces 5.2.2 SATA Interfaces These systems provide one, two, or four serial ATA (SATA) interfaces that can provide certain advantages over legacy EIDE (PATA) interface including: ■ Higher transfer rates: up to 3.0 Gb/s ■ Reduced wiring (smaller cable assemblies) The SATA interface duplicates most of the functionality of the EIDE interface through a register interface that is equivalent to that of the legacy IDE host adapter.
Input/Output Interfaces SATA Bus Master Control Registers The SATA interface can perform PCI bus master operations using the registers listed in Table 5-5. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. As indicated, these registers are virtually a copy of those used by EIDE operations discussed in the EIDE section. Table 5-5. IDE Bus Master Control Registers I/O Addr.
Input/Output Interfaces 5.3 Diskette Drive Interface The diskette drive interface in these systems support one diskette drive connected to either the MultiBay connector (USDT form factor) or to a standard 34-pin diskette drive connector (SFF, ST, MT, and CMT form factors). Selected models come standard with a 3.5-inch 1.44-MB diskette drive installed as drive A. The diskette drive interface function is integrated into the SCH5307 super I/O component.
Input/Output Interfaces Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration registers are listed in the following table: Table 5-7.
Input/Output Interfaces Diskette Drive Interface Control The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through the SCH5307's I/O-mapped registers listed in Table 5-8. The diskette drive controller of the SCH5307 operates in the PC/AT mode in these systems. Table 5-8. Diskette Drive Interface Control Registers Primary Address Second.
Input/Output Interfaces Table 5-8. (Continued) Diskette Drive Interface Control Registers Primary Address 3F4h Second.
Input/Output Interfaces 5.3.2 Diskette Drive Connector The SFF, ST, MT, and CMT form factors use a standard 34-pin connector for diskette drives (refer to Figure 5-3 and Table 5-9 for the pinout). Drive power is supplied through a separate connector. USDT form factor does not include 34-pin diskette drive connector. The diskette interface ✎ The and drive power signals are both a part of the MultiBay interface used on USDT form factors.
Input/Output Interfaces 5.4 Serial Interface Systems covered in this guide may include one RS-232-C type serial interface to transmit and receive asynchronous serial data with external devices. Some systems may allow the installation of a second serial interface through an adapter that consists of a PCI bracket and a cable that attaches to header P52 on the system board. The serial interface function is provided by the SCH5307 I/O controller component that includes two NS16C550-compatible UARTs.
Input/Output Interfaces The serial interface configuration registers are listed in the following table: Table 5-11. Serial Interface Configuration Registers Index Address Function R/W 30h Activate R/W 60h Base Address MSB R/W 61h Base Address LSB R/W 70h Interrupt Select R/W F0h Mode Register R/W Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface.
Input/Output Interfaces 5.5 Parallel Interface Systems covered in this guide may include a parallel interface for connection to a peripheral device with a compatible interface, the most common being a printer. The parallel interface function is integrated into the SCH5307 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
Input/Output Interfaces 5.5.3 Extended Capabilities Port Mode The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O.
Input/Output Interfaces Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-14 lists the parallel registers and associated functions based on mode.
Input/Output Interfaces 5.5.5 Parallel Interface Connector Figure 5-5 and Table 5-15 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port's operational mode. Figure 5-5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5-15.
Input/Output Interfaces 5.6 Keyboard/Pointing Device Interface The keyboard/pointing device interface function is provided by the SCH5307 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers. The 8042 handles scan code translation and password lock protection for the keyboard as well as communications with the pointing device.
Input/Output Interfaces Table 5-16 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5-16. 8042-To-Keyboard Commands Command Value Description Set/Reset Status Indicators EDh Enables LED indicators. Value EDh is followed by an option byte that specifies the indicator as follows: Bits <7..3> not used Bit <2>, Caps Lock (0 = off, 1 = on) Bit <1>, NUM Lock (0 = off, 1 = on) Bit <0>, Scroll Lock (0 = off, 1 = on) Echo EEh Keyboard returns EEh when previously enabled.
Input/Output Interfaces Table 5-16. (Continued) 8042-To-Keyboard Commands Command Value Description Set Keys—Make/Brake F8h Clears keyboard buffer and sets default scan code set. [1] Set Keys—Make F9h Clears keyboard buffer and sets default scan code set. [1] Set Keys— Typematic/Make/Brake FAh Clears keyboard buffer and sets default scan code set. [1] Set Type Key—Typematic FBh Clears keyboard buffer and prepares to receive key ID.
Input/Output Interfaces The keyboard interface configuration registers are listed in the following table: Table 5-17. Keyboard Interface Configuration Registers Index Address Function R/W 30h Activate R/W 70h Primary Interrupt Select R/W 72h Secondary Interrupt Select R/W F0h Reset and A20 Select R/W 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Sub-functions of INT 16 conduct the basic routines of handling keyboard data (i.e.
Input/Output Interfaces I/O Port 64h I/O port 64h is used for reading the status register and for writing commands. A read of 64h by the CPU will yield the status byte defined as follows: Bit Function 7..4 General Purpose Flags. 3 CMD/DATA Flag (reflects the state of A2 during a CPU write). 0 = Data 1 = Command 2 General Purpose Flag. 1 Input Buffer Full. Set (to 1) upon a CPU write. Cleared by IN A, DBB instruction. 0 Output Buffer Full (if set). Cleared by a CPU read of the buffer.
Input/Output Interfaces Table 5-18. (Continued) CPU Commands to the 8042 Value Command Description A9h Test the clock and data lines of the pointing device interface and place test results in the output buffer. 00h = No error detected 01h = Clock line stuck low 02h = Clock line stuck high 03h = Data line stuck low 04h = Data line stuck high AAh Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places 55h into the output buffer.
Input/Output Interfaces 5.6.4 Keyboard/Pointing Device Interface Connector The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-19 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5-7. PS/2 Keyboard or Pointing Device Interface Connector (as viewed from rear of chassis) Table 5-19.
Input/Output Interfaces 5.7 Universal Serial Bus Interface The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems. As shown in Figure 5-8, the USB interface is provided by the 82801 component.
Input/Output Interfaces 5.7.1 USB Data Formats The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a 1 is represented by no change (between bit times) in signal level and a 0 is represented by a change in signal level.
Input/Output Interfaces 5.7.2 USB Programming Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime. USB Configuration Each USB controller functions as a PCI device within the 82801 component and is configured using PCI Configuration Registers as listed in Table 5-20. NOTE: Table 5-20. USB Interface Configuration Registers PCI Config. Address Register Reset PCI Config.
Input/Output Interfaces USB Control The USB is controlled through I/O registers as listed in table 5-21. Table 5-21. USB Control Registers I/O Address Register Default Value 00, 01h Command 0000h 02, 03h Status 0000h 04, 05h Interupt Enable 0000h 06, 07 Frame Number 0000h 08, 0B Frame List Base Address 0000h 0Ch Start of Frame Modify 40h 10, 11h Port 1 Status/Control 0080h 12, 13h Port 2 Status/Control 0080h 18h Test Data 00h 5.7.
Input/Output Interfaces 5.7.4 USB Cable Data The recommended cable length between the host and the USB device should be no longer than sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following table). Table 5-23. USB Cable Length Data Conductor Size Resistance Maximum Length 20 AWG 0.036 Ω 16.4 ft (5.00 m) 22 AWG 0.057 Ω 9.94 ft (3.03 m) 24 AWG 0.091 Ω 6.82 ft (2.08 m) 26 AWG 0.145 Ω 4.30 ft (1.31 m) 28 AWG 0.232 Ω 2.66 ft (0.
Input/Output Interfaces 5.8 Audio Subsystem These systems use the HD audio controller of the 82801 component to access and control a Realtek ALC260 HD Audio Codec, which provides 2-channel high definition analog-to-digital (ADC) and digital-to-analog (DAC) conversions. A block diagram of the audio subsystem is shown in Figure 5-11. All control functions such as volume, audio source selection, and sampling rate are controlled through software through the HD Audio Interface of the 82801 ICH component.
Input/Output Interfaces 5.8.1 HD Audio Controller The HD Audio Controller is a PCI Express device that is integrated into the 82801 ICH component and supports the following functions: ■ Read/write access to audio codec registers ■ Support for greater than 48-KHz sampling ■ HD audio interface 5.8.2 HD Audio Interface The HD audio controller and the HD audio codec communicate over a five-signal HD Audio Interface (Figure 5-12).
Input/Output Interfaces 5.8.3 HD Audio Codec The HD Audio Codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13, analog audio from an external microphone, tape, or internal CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC).
Input/Output Interfaces 5.8.4 Audio Programming Audio subsystem programming consists of configuration, typically accomplished during POST, and control, which occurs during runtime. Audio Configuration The audio subsystem is configured according to PCI protocol through the HD audio controller function of the 82801 ICH. Table 5-24 lists the PCI configuration registers of the audio subsystem. Table 5-24. HD Audio Controller PCI Configuration Registers (82801 Device 27/Function 0) PCI Config.
Input/Output Interfaces Audio Control The audio subsystem is controlled through a set of verb commands listed in Table 5-25. Table 5-25. HD Audio Codec Commands Verb Value Verb Value Verb Value Get Parameter F00h Set Power State 705h Get GPIO Enable Mask F16h Get Connection Select F01h Get Conv. Stream Ch. F06h Set GPIO Enable Mask 716h Set Connection Select 701h Set Conv. Stream Ch. 706h Get GPIO Direction F17h Get Connection List F02h Get Pin Widget Cntrl.
Input/Output Interfaces 5.8.5 Audio Specifications The specifications for the HD Audio subsystem are listed in Table 5-26. Table 5-26. HD Audio Subsystem Specifications Parameter Measurement Sampling Rates: DAC ADC 44.1-, 48-, 96-, & 192-KHz [1] 44.1-, 48-, & 96-KHz [1] Resolution: DAC ADC 24-bit 20-bit Nominal Input Voltage: Mic In (w/+20 db gain) Line In .283 Vp-p 2.
Input/Output Interfaces 5.9 Network Interface Controller These systems provide 10/100/1000 Mbps network support through a Broadcom BCM5752 network interface controller (NIC), a PHY component, and a RJ-45 jack with integral status LEDs. The 82562-equivalent controller integrated into the 82801 ICH component is not used (disabled) in these systems. (Figure 5-14). The support firmware for the BCM5752 component is contained in the system (BIOS) ROM.
Input/Output Interfaces 5.9.1 Wake-On-LAN Support The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that allows the system to be booted up from a powered-down or low-power condition upon the detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power while the system unit is powered down in order to process special packets.
Input/Output Interfaces 5.9.4 NIC Programming Programming the NIC consists of configuration, which occurs during POST, and control, which occurs at runtime. The Broadcom BCM5752 is configured as a PCI device and controlled through registers mapped in variable I/O space. The BIOS for the BCM5782 is contained within the HP/Compaq BIOS in system ROM. Refer to Broadcom documentation for details regarding BCM5782 register programming. 5.9.
Input/Output Interfaces 5.9.6 NIC Specifications Table 5-27. NIC Specifications Parameter Modes Supported 10BASE-T half duplex @ 10 Mb/s 10Base-T full duplex @ 20 Mb/s 100BASE-TX half duplex @ 100 Mb/s 100Base-TX full duplex @ 200 Mb/s 1000BASE-T half duplex @ 1 Gb/s 1000BASE-TX full duplex @ 2 Gb/s Standards Compliance IEEE 802.1P, 802.1Q IEEE 802.2 IEEE 802.3, 802.3ab, 802.3ad, 802.3u, 802.3x, 802.3z OS Driver Support MS-DOS MS Windows 3.
Input/Output Interfaces 5-40 www.hp.
6 Integrated Graphics Subsystem 6.1 Introduction This chapter describes graphics subsystem that is integrated into the 82945G GMCH component. This graphics subsystem employs the use of system memory to provide efficient, economical 2D and 3D performance. The SFF, ST, MT, and CMT form factors may be upgraded by installing a graphics card into the PCI-E or the PCI 2.3 slot. The USDT form factor may be upgraded by installing an ADD2 (reverse layout) card in the PCI-E slot or a graphics card into the PCI 2.
Integrated Graphics Subsystem 6.2 Functional Description The Intel 945G GMCH component includes an integrated graphics controller (IGC). (Figure 6-1). The IGC can directly drive an external, analog multi-scan monitor at resolutions up to and including 2048 x 1536 pixels. The IGC includes a memory management feature that allocates portions of system memory for use as the frame buffer and for storing textures and 3D effects.
Integrated Graphics Subsystem The graphics controller integrated into the 82945G GMCH component includes 2D and 3D accelerator engines working with a deeply-pipelined pre-processor. Hardware cursor and overlay generators are also included as well as a legacy VGA processor core. The IGC supports three display devices: ■ One progressive-scan analog monitor ■ Up to two additional video displays with the installation of an optional Advanced Digital Display (ADD2) card in the PCI Express x16 graphics slot.
Integrated Graphics Subsystem For viewing the maximum amount of available frame buffer memory MS Windows 2000 or XP, go to Display Properties > Settings> Adapter. The Microsoft Direct diagnostic tool included in most versions of Windows may be used to check the amount of video memory being used. The Display tab of the utility the “Approx. Total Memory” label will indicate the amount of video memory. The value will vary according to OS (Windows 98 will typically show 0.
Integrated Graphics Subsystem 6.4 Upgrading Graphics The PCI-E slot of SFF, ST, MT, and CMT systems can accept a normal-layout Advanced Digital Display 2 (ADD2) or a graphics controller card. The PCI-E slot of the USDT system accepts only a reverse-layout Advanced Digital Display 2 (ADD2) card. All systems can be upgraded by installing a PCI card in the PCI 2.3 slot (assuming no riser cards are installed ).
Integrated Graphics Subsystem 6.5 VGA Monitor Connector These systems includes a standard VGA connector (Figure 6-3) for attaching an analog monitor: 9 Figure 6 3. VGA Monitor Connector, (Female DB-15, as viewed from rear). Table 6-1.
7 Power and Signal Distribution 7.1 Introduction This chapter describes the power supply and method of general power and signal distribution. Topics covered in this chapter include: 7.2 ■ Power supply assembly/control (7.2) page 7-1 ■ Power distribution (7.3) page 7-8 ■ Signal distribution (7.4) page 7-12 Power Supply Assembly/Control These systems feature a power supply assembly that is controlled through programmable logic (Figure 7-1).
Power and Signal Distribution 7.2.1 Power Supply Assembly These systems feature power supplies with power factor-correction logic. Four power supplies are used: a 200-watt power supply for the USDT unit, a 240-watt power supply for the SFF and ST units, a 300-watt power supply for the MT unit, and a 365-watt power supply for the CMT unit. All power supplies feature active power factor correction (PFC). Tables 7-1 through 7-4 list the specifications of the power supplies.
Power and Signal Distribution Table 7-3 lists the specifications for the 300-watt power supply used in the MT form factor. Table 7-3. 300-Watt (MT) Power Supply Assembly Specifications Range or Tolerance Input Line Voltage: 100–127 VAC 200–240 VAC Line Frequency Input (AC) Current +3.3 VDC Output +5.08 VDC Output +5.08 AUX Output +12 VDC Output +12 VDC Output (Vcpu) -12 VDC Output 90–132 VAC 180–264 VAC 47–63 Hz -+ 5% + 5.0% + 5.0% +5% +5% + 10 % Min. Current Loading [1] Max.
Power and Signal Distribution 7.2.2 Power Control The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When PS On is de-asserted, the Power Supply Assembly is off and no voltages (except +5 AUX) are generated. Note that the +5 AUX voltages are always produced as long as the system is connected to a live AC source.
Power and Signal Distribution Power LED Indications A dual-color LED located on the front panel (bezel) is used to indicate system power status. The front panel (bezel) power LED provides a visual indication of key system conditions listed as follows: Power LED Condition Steady green Blinks green @ 0.5 Hz Blinks red 2 times @ 1 Hz [1] Normal full-on operation Suspend state (S1) or suspend to RAM (S3) Processor thermal shut down. Check air flow, fan operation, and CPU heat sink. Processor not installed.
Power and Signal Distribution The wake up sequence for each event occurs as follows: Wake-On-LAN The network interface controller (NIC) can be configured for detection of a “Magic Packet” and wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus. Refer to Chapter 5, “Network Support” for more information. Modem Ring A ring condition on a serial port can be detected by the power control logic and, if so configured, cause the PS On signal to be asserted.
Power and Signal Distribution 7.2.3 Power Management These systems include power management functions designed to conserve energy. These functions are provided by a combination of hardware, firmware (BIOS) and software. The system provides the following power management features: ■ ACPI v2.0 compliant (ACPI modes C1, S1, and S3-S5, ) ■ APM 1.2 compliant ■ U.S. EPA Energy Star compliant Table 7-5 shows the comparison in power states. Table 7-5.
Power and Signal Distribution 7.3 Power Distribution 7.3.1 3.3/5/12 VDC Distribution The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5 VDC, +5 VDC STB, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies. Figure 7-2 shows the power supply cabling for the Ultra Slim Desktop form factor.
Power and Signal Distribution Figure 7-3 shows the power supply cabling for the SFF/ST systems. P6 1 2 3 4 P4 P5 P6 P2 P4, P5 5 4321 P3 4 P3 P2 1 Power Supply 379349 3 4 3 2 1 P1 P1 13 24 12 1 Conn 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 P1 +5 aux RTN +5 +5 PS On RTN Pwr Gd +3.3 +3.3 Tach RTN Fan P1 [1] +12 +5 sns RTN +5 +5 +3.3 RTN +3.3 sns +3.3 +3.
Power and Signal Distribution Figure 7-4 shows the power supply cabling for the microtower systems. P9, P10 P4 P5 P10 P9 P6 5 4321 P8 P2 P3 P8 P7 2 4 4 3 2 1 P7 P2-P6 3 1 Power Supply 385576 1 2 3 4 P1 P1 13 24 12 1 Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 P1 +3.3 +3.3 P1 [1] +3.3 -12 P3 RTN P4, 5, 9, 10 P6, 7, 11 RTN +5 RTN +5 RTN PS On RTN RTN RTN VccP VccP +3.3 RTN +5.
Power and Signal Distribution Figure 7-5 shows the power supply cabling for the convertible minitower systems. P9 P10 P11 P4, P5, P9, P10 P6 P7 P8 5 4321 P8 P4 P5 P3 2 4 4 3 2 1 P3 P6, P7, P11 3 1 Power Supply 379294 1 2 3 4 P1 P1 13 24 12 1 Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 P1 +3.3 +3.3 P1 [1] +3.3 -12 P3 RTN P4, 5, 9, 10 P6, 7, 11 RTN +5 RTN +5 RTN PS On RTN RTN RTN VccP VccP +3.3 RTN +5.
Power and Signal Distribution 7.3.2 Low Voltage Production/Distribution Auxiliary voltages less than 5 volts and all voltages less than 3.3 volts are produced through regulator circuitry (Figure 7-6) on the system board. CPU 12 VDC PS Regulator Circuit VccP 5 VDC PS 5 VDC PS 5 VDC 5 VDC Switch 1.8 VDC 1.8 V Regulator Power Supply 0.9 V Regulator 5 Aux PS 0.9 VDC 5 Aux PS Aux Regulator Processor PCI, SATA, LPT, COM, Diskette logic USB, PS2 Kybd Chipset, DIMMs DIMMs Chipset 3.3 VDC AUX 2.
Power and Signal Distribution 7.4 Signal Distribution Figures 7-7 through 7-9 show general signal distribution between the main subassemblies of the system units. Chassis Fan Speaker Power On Power LED P8 HD LED P6 P5 P3 +12 VccP +3.3, +5, +5 Aux, +12 VDC P1 System Board 376335-001 P60 P21 PS On, POK SATA I/F IDE I/F., Diskette I/F.
Power and Signal Distribution Chassis Fan Speaker Power On Power LED P8 HD LED P6 P5 +12 VccP P3 +3.3, +5, +5 Aux, +12 VDC P1 PS On, POK Diskette I/F P10 System Board 376332-001 P60 SATA I/F Diskette SATA Hard Drive CD-ROM IDE I/F P20 Power Supply Assembly Keyboard Kybd data J66 Mouse data J67 P23 P24 Mouse Mic In, HP Out Audio USB 6,7 Tx/Rx Front Panel I/O Module NOTES: See Figure 7-7 for header pinout. Figure 7-8. SFF / ST Form Factor Signal Distribution Diagram 7-14 www.hp.
Power and Signal Distribution Chassis Fan Speaker Power On Power LED P8 HD LED P6 P5 P3 +12 VccP +3.3, +5, +5 Aux, +12 VDC P1 P10 System Board 375374-001 P60 P20 PS On, POK Diskette I/F SATA I/F IDE I/F. Power Supply Assembly Diskette SATA Hard Drive CD-ROM Keyboard Kybd data J68 P23 P24 Mouse data Mouse Mic In, HP Out Audio USB 6,7 Tx/Rx Front Panel I/O Module J30 PCI 2.3 I/F PCI Expansion Daughter Board [1] NOTE: [1] CMT form factor only. Figure 7-9.
Power and Signal Distribution Power Button/LED, HD LED Header P5 (USDT, SFF, ST) HD LED Cathode 1 HD LED Anode 3 2 PS LED Cathode 4 PS LED Anode GND5 Chassis ID0 9 GND 11 Power Button/LED, HD LED Header P5 (MT, CMT) 6 Pwr Btn 8 GND GND5 M Reset 7 10 Chassis ID1 12 NC +5 VDC 9 14 Therm Diode C Therm Diode A 13 Aux Audio NC 11 GND 13 Chassis ID2 15 12 GND Chassis ID0 17 18 Chassis ID1 16 +5 VDC 2 Analog GND Mic In Sleeve 3 HP Out Right 5 4 NC 6 Headphone sense Front Audio Detect 7 HP Out L
8 BIOS ROM 8.1 Introduction The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug 'n Play support, power management activities, and the Setup utility. The firmware contained in the BIOS ROM supports the following operating systems and specifications: ■ DOS 6.2 ■ Windows 3.
BIOS ROM 8.2 ROM Flashing The system BIOS firmware is contained in a flash ROM device that can be re-written with new BIOS code using a flash utility locally (with F10 setup), with the HPQFlash program in a Windows environment, or with the FLASHBIN.EXE utility in a DOS or DOS-like environment. 8.2.1 Upgrading Upgrading the BIOS is not normally required but may be necessary if changes are made to the unit's operating system, hard drive, or processor. All BIOS ROM upgrades are available directly from HP.
BIOS ROM 8.2.2 Changeable Splash Screen corrupted splash screen may be restored by reflashing the BIOS image through F10 setup, ✎ Arunning HPQFlash, or running FLASHBIN.EXE. Depending on the system, changing (customizing) the splash screen may only be available with asistance from HP. The splash screen (image displayed during POST) is stored in the BIOS ROM and may be replaced with another image of choice by using the Image Flash utility (Flashi.exe).
BIOS ROM 8.3.2 Network Boot (F12) Support The BIOS supports booting the system to a network server. The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST. Booting to a network server allows for such functions as: ■ Flashing a ROM on a system without a functional operating system (OS). ■ Installing an OS. ■ Installing an application.
BIOS ROM 8.3.4 Boot Error Codes The BIOS provides visual and audible indications of a failed system boot by using the system’s power LED and the system board speaker. The error conditions are listed in the following table. Table 8-1 Boot Error Codes Visual (power LED) Audible (speaker) Meaning Blinks red 2 times @ 1 Hz None Processor thermal shut down. Check air flow, fan operation, and CPU heat sink. Blinks red 3 times @ 1 Hz None Processor not installed. Install or reseat CPU.
BIOS ROM 8.4 Setup Utility The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the F10 key is pressed and held during the computer boot cycle. Highlights of the Setup utility are described in the following table. pressing and releasing the computer’s power button, press and hold the F10 key until the ✎ After Setup Utility screen is displayed.
BIOS ROM Table 8-2 Setup Utility Heading File (continued) Storage Option Description Ignore Changes and Exit Exits Computer Setup without applying or saving any changes. Save Changes and Exit Saves changes to system configuration or default settings and exits Computer Setup. Device Configuration Lists all installed BIOS-controlled storage devices. When a device is selected, detailed information and options are displayed. The following options may be presented.
BIOS ROM Table 8-2 Setup Utility Heading File (continued) Storage Option Description Ignore Changes and Exit Exits Computer Setup without applying or saving any changes. Save Changes and Exit Saves changes to system configuration or default settings and exits Computer Setup. Device Configuration Lists all installed BIOS-controlled storage devices. When a device is selected, detailed information and options are displayed. The following options may be presented.
BIOS ROM Table 8-2 Setup Utility Heading Option Description Transfer Mode Storage (continued) Specifies mode used for data transfer.. Options (subject to device capabilities) are Max UDMA (default), PIO 0, Max PIO, Enhanced DMA, and Ultra DMA 0. Translation Parameters (ATA disks only) This feature appears only when User translation mode is selected.
BIOS ROM Table 8-2 Setup Utility Heading Option Description IDE Controller Storage (continued) Allows you to enable or disable the primary IDE controller. This feature is supported on select models only. Primary SATA Controller Allows you to enable or disable the Primary SATA controller. Secondary SATA Controller Allows you to enable or disable the Secondary SATA controller. This feature is supported on select models only.
BIOS ROM Table 8-2 Setup Utility Heading Security (continued) Option Description Password Options (This selection will appear only if a power-on password is set.) Allows you to specify whether the password is required for warm boot (CTRL+ALT+DEL). Smart Cover Allows you to: Lock Legacy Resources - When enabled, prevents operating system from changing legacy resources. • Lock/unlock the Cover Lock. • Set the Cover Removal Sensor to Disable/Notify User/Setup Password.
BIOS ROM Table 8-2 Setup Utility Heading Security Option Description DriveLock Security Allows you to assign or modify a master or user password for hard drives that support the ATA security command set. When this feature is enabled, the user is prompted to provide one of the DriveLock passwords during POST. If neither is successfully entered, the hard drive will remain inaccessible until one of the passwords is successfully provided during a subsequent cold-boot sequence.
BIOS ROM Table 8-2 Setup Utility Heading Advanced* Option Power-On Options *For advanced users only Description Allows you to set: • POST mode (QuickBoot, FullBoot, or FullBoot every 1-30 days). • POST messages (enable/disable). • F9 prompt (enable/disable). Enabling this feature will display the text F9=Boot Menu during POST. Disabling this feature prevents the text from being displayed but pressing F9 will still access the Shortcut Boot (Order) Menu screen.
BIOS ROM Table 8-2 Setup Utility Heading Advanced* (continued) Option Power-On Options (continued) *For advanced users only Description Allows you to set: (continued) • ACPI/USB Buffers @ Top of Memory (enable/disable). Enabling this feature places USB memory buffers at the top of memory. The advantage is that some amount of memory below 1 MB is freed up for use by option ROMs. The disadvantage is that a popular memory manager, HIMEM.
BIOS ROM Table 8-2 Setup Utility Heading Advanced* (continued) Option Device options Description Allows you to set: • Printer mode (bi-directional, EPP & ECP, output only). *For advanced users only • Num Lock state at power-on (off/on). • S5 Wake on LAN (enable/disable). • To disable Wake on LAN during the off state (S5), use the arrow (left and right) keys to select the Advanced > Device Options menu and set the S5 Wake on Lan feature to “Disable.
BIOS ROM 8.5 Client Management Functions Table 8-3 provides a partial list of the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaq-specific unless otherwise indicated. Table 8-3. Client Management Functions (INT15) AX Function Mode E800h Get system ID Real, 16-, & 32-bit Prot. E813h Get monitor data Real, 16-, & 32-bit Prot. E814h Get system revision Real, 16-, & 32-bit Prot.
BIOS ROM 8.5.1 System ID and ROM Type Diagnostic applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register. systems have the following IDs and ROM family types: Table 8-4 System ID System (Form Factor) System ID USDT 09FCh SFF/ST: 09F8h uT: 09F4h CMT: 09F0h NOTE: All systems use BIOS ROM Family 786D1 and have a PnP ID of CPQ0968.
BIOS ROM 8.6 SMBIOS In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS version 2.
A Error Messages and Codes A.1 Introduction This appendix lists the error codes and a brief description of the probable cause of the error. ✎ Errors listed in this appendix are applicable only for systems running HP/Compaq BIOS. Not all errors listed in this appendix may be applicable to a particular system model and/or configuration. A.2 Beep/Power LED Codes ✎ Beep and Power LED indictions listed in Table A-1 apply only to HP-branded models. Table A-1.
Error Messages and Codes A.3 Power-On Self Test (POST) Messages Table A-2. Power-On Self Test (POST) Messages Error Message Probable Cause Invalid Electronic Serial Number Chassis serial number is corrupt. Use Setup to enter a valid number. Network Server Mode Active (w/o kybd) System is in network mode. 101-Option ROM Checksum Error A device’s option ROM has failed/is bad. 110-Out of Memory Space for Option ROMs Recently added PCI card contains and option ROM too large to download during POST.
Error Messages and Codes Table A-2. (Continued) Power-On Self Test (POST) Messages Error Message Probable Cause 512-Chassis Fan Not Detected Chassis fan is not connected. 514-CPU or Chassis Fan not detected. CPU fan is not connected or may have malfunctioned. 601-Diskette Controller Error Diskette drive removed since previous boot. 605-Diskette Drive Type Error Mismatch in drive type.
Error Messages and Codes Table A-2. (Continued) Power-On Self Test (POST) Messages A-4 Error Message Probable Cause 1801-Microcode Patch Error A processor is installed for which the BIOS ROM has no patch. Check for ROM update. Invalid Electronic Serial Number Electronic serial number has become corrupted. Network Server Mode Active and No Keyboard Attached Keyboard failure while Network Server Mode enabled. Parity Check 2 Keyboard failure while Network Server Mode enabled. www.hp.
Error Messages and Codes A.4 System Error Messages (1xx-xx) Table A-3. System Error Messages Message Probable Cause Message Probable Cause 101 Option ROM error 109-02 CMOS clock rollover test failed 102 System board failure 109-03 CMOS not properly initialized (clk test) 103 System board failure 110-01 Programmable timer load data test failed 104-01 Master int. cntlr. test fialed 110-02 Programmable timer dynamic test failed 104-02 Slave int. cntlr.
Error Messages and Codes A.5 Memory Error Messages (2xx-xx) Table A-4.
Error Messages and Codes Table A-4. (Continued) Memory Error Messages Message Probable Cause 211-02 Error while saving memory during random memory pattern test 211-03 Error while restoring memory during random memory pattern test 213-xx Incompatible DIMM in slot x 214-xx Noise test failed 215-xx Random address test A.6 Keyboard Error Messages (30x-xx) Table A-5.
Error Messages and Codes A.7 Printer Error Messages (4xx-xx) Table A-6 Printer Error Messages Message Probable Cause Message Probable Cause 401-01 Printer failed or not connected 402-11 Interrupt test, data/cntrl. reg. failed 402-01 Printer data register failed 402-12 Interrupt test and loopback test failed 402-02 Printer control register failed 402-13 Int. test, LpBk. test., and data register failed 402-03 Data and control registers failed 402-14 Int. test, LpBk. test., and cntrl.
Error Messages and Codes A.9 Diskette Drive Error Messages (6xx-xx) Table A-8.
Error Messages and Codes A.10 Serial Interface Error Messages (11xx-xx) Table A-9. Serial Interface Error Messages Message Probable Cause Message Probable Cause 1101-01 UART DLAB bit failure 1101-13 UART cntrl. signal interrupt failure 1101-02 Line input or UART fault 1101-14 DRVR/RCVR data failure 1101-03 Address line fault 1109-01 Clock register initialization failure 1101-04 Data line fault 1109-02 Clock register rollover failure 1101-05 UART cntrl.
Error Messages and Codes A.11 Modem Communications Error Messages (12xx-xx) Table A-10.
Error Messages and Codes Table A-10.
Error Messages and Codes A.13 Hard Drive Error Messages (17xx-xx) Table A-12 Hard Drive Error Messages Message Probable Cause Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-51 Failed I/O read test 17xx-02 Exceeded max. Hard error limit 17xx-52 Failed file I/O compare test 17xx-03 Previously exceeded max. soft error limit 17xx-53 Failed drive/head register test 17xx-04 Previously exceeded max.
Error Messages and Codes NOTE: xx = 00, Hard drive ID test xx = 19, Hard drive power mode test xx = 01, Hard drive format test xx = 20, SMART drive detects imminent failure xx = 02, Hard drive read test xx = 21, SCSI hard drive imminent failure xx = 03, Hard drive read/write compare test xx = 24, Net work preparation test xx = 04, Hard drive random seek test xx = 36, Drive monitoring test xx = 05, Hard drive controller test xx = 71, Pri.
Error Messages and Codes A.
Error Messages and Codes A.
Error Messages and Codes A.17 DVD/CD-ROM Error Messages (33xx-xx) Table A-16 DVD/CD-ROM Error Messages Message Probable Cause 3301-xx Drive test failed 3305-xx Seek test failed A.
Error Messages and Codes A.
Error Messages and Codes A.
Error Messages and Codes A-20 www.hp.
B ASCII Character Set B.1 Introduction This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol. The extended ASCII characters (decimals 128-255) can only be called using the Alt + Numeric Keypad keys.
ASCII Character Set Table B-1.
ASCII Character Set Table B-1.
ASCII Character Set B-4 www.hp.
C Keyboard C.1 Introduction This appendix describes the HP keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions. This appendix covers the following keyboard types: ■ Standard enhanced keyboard.
Keyboard Num Lock Caps Lock Matrix Drivers Keyswitch Matrix Scroll Lock Data/ CLK Matrix Receivers Keyboard Processor Keyboard Interface (System Unit) Figure C-1. Keystroke Processing Elements, Block Diagram When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT) that checks for shorted keys and basic operation of the keyboard processor.
Keyboard C.2.1 PS/2-Type Keyboard Transmissions The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer.
Keyboard C.2.2 USB-Type Keyboard Transmissions The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide). Packets received at the system's USB I/F and decoded as originating from the keyboard result in an SMI being generated.
Keyboard C.2.3.2 Windows Enhanced Keyboards 1 18 17 3 4 5 19 20 21 22 40 39 59 41 60 75 92 6 2 42 61 76 43 62 77 23 44 63 78 45 79 25 46 65 80 93 110 24 64 8 7 26 47 66 81 9 27 11 28 29 68 83 94 30 51 14 15 16 32 33 34 35 36 37 52 53 54 55 56 57 72 73 74 88 89 90 71 87 86 85 95 13 31 70 69 84 12 50 48 49 67 82 10 96 111 112 97 98 99 100 101 38 58 91 Figure C-5. U.S.
Keyboard C.2.3.3 Easy Access Keyboard The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. The Easy Access Keyboard uses the PS/2-type connection. Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8 ✎ Main key positions same as Windows Enhanced (Figures C-5 or C-6). Figure C-7. 8-Button Easy Access Keyboard Layout C-6 www.hp.
Keyboard C.2.4 Keys All keys generate a Make code (when pressed) and a Break code (when released) with the exception of the Pause key (pos. 16), which produces a Make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
Keyboard Alt—The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position 16 (Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-57, 72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The application determines the actual function of the keystrokes. Both Alt key positions provide identical functionality.
Keyboard C.2.4.4 Easy Access Keystrokes The Easy Access keyboards(Figures C-7) include additional keys (also referred to as buttons) used to streamline internet access and navigation.
Keyboard C.2.5 Keyboard Commands Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042-type logic). Table C-1. Keyboard-to-System Commands Command Value Description Key Detection Error/Over/run 00h [1] Indicates to the system that a switch closure FFh [2] couldn’t be identified. BAT Completion AAh Indicates to the system that the BAT has been successful. BAT Failure FCh Indicates failure of the BAT by the keyboard.
Keyboard C.2.6 Scan Codes The scan codes generated by the keyboard processor are determined by the mode the keyboard is operating in. ■ Mode 1: In Mode 1 operation, the keyboard generates scan codes compatible with 8088-/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard controller must be disabled. Since translation is not performed, the scan codes generated in Mode 1 are identical to the codes required by BIOS.
Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Key Pos.
Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Key Pos.
Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Key Pos.
Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Key Pos.
Keyboard Table C-2. (Continued) Keyboard Scan Codes Key Pos.
Keyboard C.3 Connectors Two types of keyboard interfaces may be used in HP/Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to Chapter 5 “Input/Output” of this guide.
Keyboard C-18 www.hp.
Index Numerics 8259 Mode 4-12 A Advanced Digital Display (ADD2) 6-2 APIC Mode 4-13 audible (beep) indications 4-23 audio codec 5-32 Audio Specifications 5-35 B beep indications 4-23 BIOS upgrading 8-2 boot device order 8-3 Boot Error Codes 8-5 C CMOS 4-19 CMOS, clearing 4-9 Computer Setup 8-6 configuration memory 4-19 D Direct Memory Access (DMA) 4-16 Diskette Drive Connector 5-11 diskette drive interface 5-7 F G graphics subsystem 6-1 H HD Audio Controller 5-31 header pinouts 7-15 Technical Reference Gui
Index S SATA 4-1 SATA Connector 4-6 SDVO 6-2 serial interface 5-12 Serial Interface Connector 5-12 serial number 1-3 Setup utility 8-6 Smart Cover Lock 2-22 Smart Cover Sensor 2-21 SMBIOS 8-18 SPD address map 3-6 specifications physical 2-26 system ID 8-17 T Temperature Status 8-17 U Universal Serial Bus (USB) interface 5-25 upgrading BIOS 8-2 upgrading graphics 6-5 USB 5-25 V VGA connector 6-6 W Web sites Adobe Systems, Inc.
