HP StorageWorks Fabric OS 6.2 administrator guide (5697-0016, May 2009)

Fabric OS 6.2 administrator guide 467
Constraints for FCIP Fastwrite and Tape Pipelining
Consider the constraints described in Table 95 when configuring tunnels to use either of these features.
FCIP Fastwrite and Tape Pipelining configurations
To help understand the supported configurations, consider the configurations shown in the two figures
below. In both cases, there are no multiple equal-cost paths. In Figure 79, there is a single tunnel with
Fastwrite and Tape Pipelining enabled. In Figure 80, there are multiple tunnels, but none of them create a
multiple equal-cost path.
Figure 79 Single tunnel, Fastwrite and Tape Pipelining enabled
Table 95 Using FCIP Fastwrite and Tape Pipelining
FCIP Fastwrite Tape pipelining
Each GbE port supports up to 2048 simultaneous
accelerated exchanges, which means a total of
2048 simultaneous exchanges combined for
Fastwrite and Tape Pipelining.
Each GbE port supports up to 2048 simultaneous
accelerated exchanges, which means a total of
2048 simultaneous exchanges combined for
Fastwrite and Tape Pipelining.
Does not affect FICON traffic Does not affect FICON traffic
FCIP Fastwrite and FC Fastwrite are mutually
exclusive.
Tape pipelining uses FCIP Fastwrite, not FC
Fastwrite.
Does not support multiple equal-cost path
configurations (see ”FCIP Fastwrite and Tape
Pipelining configurations”).
Does not support multiple equal-cost path
configurations or multiple non-equal-cost path
configurations (see ”FCIP Fastwrite and Tape
Pipelining configurations”).
Class 3 traffic is accelerated with Fastwrite. Class 3 traffic is accelerated between host and
sequential device.
With sequential devices (tape drives), there are
1024 initiator-tape (IT) pairs per GbE port, but
2048 initiator-tape-LUN (ITL) pairs per GbE port.
The ITL pairs are shared among the IT pairs. For
example:
Two ITL pairs for each IT pair as long as the target
has two LUNs.
If a target has 32 LUNs, 32 ITL pairs for IT pairs. In
this case, only 64 IT pairs are associated with ITL
pairs.
The rest of the IT pairs are not associated to any ITL
pairs, so no Tape Pipelining is performed for those
pairs. By default, only Fastwrite-based acceleration
is performed on the unassociated pairs.
Does not support multiple non-equal-cost path
between host and sequential device
Connection can be
VE-VE or VEX-VE